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PIC18F6393 Datasheet(PDF) 21 Page - Microchip Technology |
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PIC18F6393 Datasheet(HTML) 21 Page - Microchip Technology |
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21 / 58 page ![]() © 2009 Microchip Technology Inc. DS39896B-page 21 PIC18F6393/6493/8393/8493 TABLE 1-3: PIC18F8X93 PINOUT I/O DESCRIPTIONS Pin Name Pin Number Pin Type Buffer Type Description TQFP MCLR/VPP/RG5 MCLR VPP RG5 9 I P I ST ST Master Clear (input) or programming voltage (input). Master Clear (Reset) input. This pin is an active-low Reset to the device. Programming voltage input. Digital input. OSC1/CLKI/RA7 OSC1 CLKI RA7 49 I I I/O ST CMOS TTL Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. External clock source input. Always associated with pin function OSC1. (See related OSC1/CLKI, OSC2/CLKO pins.) General purpose I/O pin. OSC2/CLKO/RA6 OSC2 CLKO RA6 50 O O I/O — — TTL Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. General purpose I/O pin. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) Note 1: Default assignment for CCP2 when Configuration bit, CCP2MX, is set. 2: Alternate assignment for CCP2 when Configuration bit, CCP2MX, is cleared. |
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