PIC16F688-ISLASHML datasheet(121/204 Pages) MICROCHIP

121 / 204 page

DS41203E-page 119

PIC16F688

11.3

Interrupts

The PIC16F688 has multiple sources of interrupt:

• External Interrupt RA2/INT

• TMR0 Overflow Interrupt

• PORTA Change Interrupts

• 2 Comparator Interrupts

• A/D Interrupt

• Timer1 Overflow Interrupt

• EEPROM Data Write Interrupt

• Fail-Safe Clock Monitor Interrupt

• EUSART Receive and Transmit interrupts

The Interrupt Control (INTCON) register and Peripheral

Interrupt Request 1 (PIR1) register record individual

interrupt requests in flag bits. The INTCON register

also has individual and global interrupt enable bits.

A Global Interrupt Enable bit, GIE bit of the INTCON

ables (if cleared) all interrupts. Individual interrupts can

be disabled through their corresponding enable bits in

the INTCON register and PIE1 register. GIE is cleared

on Reset.

The Return from Interrupt instruction, RETFIE, exits

the interrupt routine, as well as sets the GIE bit, which

re-enables unmasked interrupts.

The following interrupt flags are contained in the

INTCON register:

• INT Pin Interrupt

• PORTA Change Interrupt

• TMR0 Overflow Interrupt

The peripheral interrupt flags are contained in the

special register, PIR1. The corresponding interrupt

enable bit is contained in special register, PIE1.

The following interrupt flags are contained in the PIR1

• EEPROM Data Write Interrupt

• A/D Interrupt

• EUSART Receive and Transmit Interrupts

• 2 Comparator Interrupts

• Timer1 Overflow Interrupt

• Fail-Safe Clock Monitor Interrupt

When an interrupt is serviced:

• The GIE is cleared to disable any further interrupt.

• The return address is pushed onto the stack.

• The PC is loaded with 0004h.

For external interrupt events, such as the INT pin or

PORTA change interrupt, the interrupt latency will be

three or four instruction cycles. The exact latency

depends upon when the interrupt event occurs (see

Figure 11-8). The latency is the same for one or

two-cycle instructions. Once in the Interrupt Service

Routine, the source(s) of the interrupt can be

determined by polling the interrupt flag bits. The

interrupt flag bit(s) must be cleared in software before

re-enabling interrupts to avoid multiple interrupt

requests.

For additional information on Timer1, A/D or data

EEPROM modules, refer to the respective peripheral

section.

Note 1: Individual interrupt flag bits are set,

regardless

the

status

their

corresponding mask bit or the GIE bit.

2: When an instruction that clears the GIE

bit is executed, any interrupts that were

pending for execution in the next cycle

are ignored. The interrupts, which were

ignored, are still pending to be serviced

when the GIE bit is set again.

PIC16F688-I/ML Datasheet(PDF) 121 Page - Microchip Technology

PIC16F688-I/ML Datasheet(HTML) 121 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL