PIC16F688-ISLASHML datasheet(125/204 Pages) MICROCHIP

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DS41203E-page 123

PIC16F688

11.5

Watchdog Timer (WDT)

The WDT has the following features:

• Operates from the LFINTOSC (31 kHz)

• Contains a 16-bit prescaler

• Shares an 8-bit prescaler with Timer0

• Time-out period is from 1 ms to 268 seconds

• Configuration bit and software controlled

WDT is cleared under certain conditions described in

Table 11-7.

11.5.1

WDT OSCILLATOR

The WDT derives its time base from the 31 kHz

LFINTOSC. The LTS bit does not reflect that the

LFINTOSC is enabled.

The value of WDTCON is ‘---0 1000’ on all Resets.

This gives a nominal time base of 16 ms, which is

compatible with the time base generated with previous

PIC16F688 microcontroller versions.

A new prescaler has been added to the path between

the INTRC and the multiplexers used to select the path

for the WDT. This prescaler is 16 bits and can be

programmed to divide the INTRC by 32 to 65536,

giving the WDT a nominal range of 1 ms to 268s.

11.5.2

WDT CONTROL

The WDTE bit is located in the Configuration Word

When the WDTE bit in the Configuration Word register

is set, the SWDTEN bit of the WDTCON register has no

effect. If WDTE is clear, then the SWDTEN bit can be

used to enable and disable the WDT. Setting the bit will

enable it and clearing the bit will disable it.

The PSA and PS<2:0> bits of the OPTION register

have the same function as in previous versions of the

PIC16F688 family of microcontrollers. See Section 5.0

“Timer0 Module” for more information.

FIGURE 11-9:

WATCHDOG TIMER BLOCK DIAGRAM

Note:

When the Oscillator Start-up Timer (OST)

is invoked, the WDT is held in Reset,

because the WDT Ripple Counter is used

by the OST to perform the oscillator delay

count. When the OST count has expired,

the WDT will begin counting (if enabled).

TABLE 11-7:

WDT STATUS

Conditions

WDT

WDTE = 0

Cleared

CLRWDT

Command

Oscillator Fail Detected

Exit Sleep + System Clock = T1OSC, EXTRC, INTRC, EXTCLK

Exit Sleep + System Clock = XT, HS, LP

Cleared until the end of OST

31 kHz

PSA

16-bit WDT Prescaler

From TMR0 Clock Source

Prescaler(1)

PS<2:0>

PSA

WDT Time-out

To TMR0

WDTPS<3:0>

WDTE from Configuration Word Register

SWDTEN from WDTCON

LFINTOSC Clock

Note 1: This is the shared Timer0/WDT prescaler. See Section 5.1.3 “Software Programmable Prescaler” for more information.

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