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PIC18F4580-E/ML Datasheet(PDF) 484 Page - Microchip Technology |
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PIC18F4580-E/ML Datasheet(HTML) 484 Page - Microchip Technology |
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484 / 490 page  PIC18F2480/2580/4480/4580 DS39637D-page 484 © 2009 Microchip Technology Inc. PR2 Register .................................................... 173, 179 TMR2 to PR2 Match Interrupt .......................... 173, 179 Timer3 .............................................................................. 163 16-Bit Read/Write Mode ........................................... 165 Associated Registers ....................................... 165, 172 Operation ................................................................. 164 Oscillator .......................................................... 163, 165 Overflow Interrupt ............................................ 163, 165 Special Event Trigger (CCP) .................................... 165 TMR3H Register ...................................................... 163 TMR3L Register ....................................................... 163 Timing Diagrams A/D Conversion ........................................................ 457 Acknowledge Sequence .......................................... 224 Asynchronous Reception ......................................... 245 Asynchronous Transmission .................................... 242 Asynchronous Transmission (Back-to-Back) ........... 242 Automatic Baud Rate Calculation ............................ 240 Auto-Wake-up Bit (WUE) During Normal Operation ............................................. 246 Auto-Wake-up Bit (WUE) During Sleep ................... 246 Baud Rate Generator with Clock Arbitration ............ 218 BRG Overflow Sequence ......................................... 240 BRG Reset Due to SDA Arbitration During Start Condition ................................................. 227 Brown-out Reset (BOR) ........................................... 443 Bus Collision During a Repeated Start Condition (Case 1) ........................................... 228 Bus Collision During a Repeated Start Condition (Case 2) ........................................... 228 Bus Collision During a Start Condition (SCL = 0) ......................................................... 227 Bus Collision During a Start Condition (SDA only) ........................................................ 226 Bus Collision During a Stop Condition (Case 1) ........................................................... 229 Bus Collision During a Stop Condition (Case 2) ........................................................... 229 Bus Collision for Transmit and Acknowledge ........... 225 Capture/Compare/PWM (CCP) ................................ 445 CLKO and I/O .......................................................... 442 Clock Synchronization ............................................. 211 EUSART Synchronous Receive (Master/Slave) ...... 455 EUSART Synchronous Transmission (Master/Slave) .................................................. 455 Example SPI Master Mode (CKE = 0) ..................... 447 Example SPI Master Mode (CKE = 1) ..................... 448 Example SPI Slave Mode (CKE = 0) ....................... 449 Example SPI Slave Mode (CKE = 1) ....................... 450 External Clock (All Modes except PLL) .................... 440 Fail-Safe Clock Monitor ............................................ 362 First Start Bit Timing ................................................ 219 Full-Bridge PWM Output .......................................... 183 Half-Bridge PWM Output ......................................... 182 High-Voltage Detect (VDIRMAG = 1) ....................... 276 I2C Bus Data ............................................................ 451 I2C Bus Start/Stop Bits ............................................. 451 I2C Master Mode (7 or 10-Bit Transmission) ........... 222 I2C Master Mode (7-Bit Reception) .......................... 223 I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 208 I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 213 I2C Slave Mode (10-Bit Transmission) ..................... 209 I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 206 I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 212 I2C Slave Mode (7-Bit Transmission) ....................... 207 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Address Mode) ............................. 214 Low-Voltage Detect (VDIRMAG = 0) ....................... 275 Master SSP I2C Bus Data ........................................ 453 Master SSP I2C Bus Start/Stop Bits ........................ 453 Parallel Slave Port (PIC18F4480/4580) ................... 446 Parallel Slave Port (PSP) Read ............................... 150 Parallel Slave Port (PSP) Write ............................... 150 PWM Auto-Shutdown (PRSEN = 0, Auto-Restart Disabled) .................................... 188 PWM Auto-Shutdown (PRSEN = 1, Auto-Restart Enabled) ..................................... 188 PWM Direction Change ........................................... 185 PWM Direction Change at Near 100% Duty Cycle ............................................. 185 PWM Output ............................................................ 173 Repeat Start Condition ............................................ 220 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ..... 443 Send Break Character Sequence ............................ 247 Slave Synchronization ............................................. 197 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 53 SPI Mode (Master Mode) ......................................... 196 SPI Mode (Slave Mode with CKE = 0) ..................... 198 SPI Mode (Slave Mode with CKE = 1) ..................... 198 Stop Condition Receive or Transmit Mode .............. 224 Synchronous Reception (Master Mode, SREN) ...... 250 Synchronous Transmission ..................................... 248 Synchronous Transmission (Through TXEN) .......... 249 Time-out Sequence on POR w/ PLL Enabled (MCLR Tied to VDD) ............................ 53 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ...................... 52 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ...................... 52 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise Tpwrt) ................ 52 Timer0 and Timer1 External Clock .......................... 444 Transition for Entry to Idle Mode ................................ 44 Transition for Entry to SEC_RUN Mode .................... 41 Transition for Entry to Sleep Mode ............................ 43 Transition for Two-Speed Start-up (INTOSC to HSPLL) ........................................ 360 Transition for Wake From Idle to Run Mode .............. 44 Transition for Wake From Sleep (HSPLL) ................. 43 Transition From RC_RUN Mode to PRI_RUN Mode ................................................. 42 Transition From SEC_RUN Mode to PRI_RUN Mode (HSPLL) .................................. 41 Transition to RC_RUN Mode ..................................... 42 Timing Diagrams and Specifications ............................... 440 A/D Conversion Requirements ................................ 457 AC Characteristics Internal RC Accuracy ....................................... 441 Capture/Compare/PWM Requirements ................... 445 CLKO and I/O Requirements ................................... 442 EUSART Synchronous Receive Requirements ....... 455 EUSART Synchronous Transmission Requirements .................................................. 455 |
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