PIC18F4580-ESLASHML datasheet(171/490 Pages) MICROCHIP

171 / 490 page

DS39637D-page 171

PIC18F2480/2580/4480/4580

16.3

Compare Mode

In Compare mode, the 16-bit CCPR1 register value is

constantly compared against either the TMR1 or TMR3

pin can be:

• driven high

• driven low

• toggled (high-to-low or low-to-high)

• remain unchanged (that is, reflects the state of the

I/O latch)

The action on the pin is based on the value of the mode

select bits (ECCP1M<3:0>). At the same time, the

interrupt flag bit, ECCP1IF, is set.

16.3.1

CCP PIN CONFIGURATION

The user must configure the CCP1 pin as an output by

clearing the appropriate TRIS bit.

16.3.2

TIMER1/TIMER3 MODE SELECTION

Timer1 and/or Timer3 must be running in Timer mode

or Synchronized Counter mode if the CCP module is

using the compare feature. In Asynchronous Counter

mode, the compare operation may not work.

16.3.3

SOFTWARE INTERRUPT MODE

When the Generate Software Interrupt mode is chosen

(CCP1M<3:0> = 1010), the CCP1 pin is not affected.

Only a CCP interrupt is generated, if enabled, and the

CCP1IE bit is set.

16.3.4

SPECIAL EVENT TRIGGER

Both CCP modules are equipped with a Special Event

Trigger. This is an internal hardware signal generated

in Compare mode to trigger actions by other modules.

The Special Event Trigger is enabled by selecting

the Compare

Special

Event

Trigger

mode

(CCP1M<3:0> = 1011).

For either CCP module, the Special Event Trigger

resets the Timer register pair for whichever timer

resource is currently assigned as the module’s time

base. This allows the CCPR1 registers to serve as a

programmable period register for either timer.

FIGURE 16-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

Note:

Clearing the CCP1CON register will force

the RC2 compare output latch (depending

on device configuration) to the default low

level. This is not the PORTC I/O data

latch.

CCPR1H

CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set CCP1IF

CCP1 pin

TRIS

CCP1CON<3:0>

Output Enable

TMR3H

TMR3L

ECCPR1H

ECCPR1L

Comparator

T3ECCP1

T3CCP1

Set CCP1IF

Compare

(Timer1 Reset)

Output

Logic

Special Event Trigger

ECCP1 pin

TRIS

ECCP1CON<3:0>

Output Enable

(Timer1/Timer3 Reset, A/D Trigger)

Match

Compare

Match

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