PIC18F4580-ESLASHML datasheet(174/490 Pages) MICROCHIP

174 / 490 page

PIC18F2480/2580/4480/4580

DS39637D-page 174

The CCPR1H register and a 2-bit internal latch are

used to double-buffer the PWM duty cycle. This

double-buffering is essential for glitchless PWM

operation.

When the CCPR1H and 2-bit latch match TMR2,

concatenated with an internal 2-bit Q clock or 2 bits of

the TMR2 prescaler, the CCP1 pin is cleared.

The maximum PWM resolution (bits) for a given PWM

frequency is given by the equation.

EQUATION 16-3:

TABLE 16-4:

EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz

16.4.3

PWM AUTO-SHUTDOWN

(ECCP1 ONLY)

The PWM auto-shutdown features of the Enhanced

CCP

module

are

available

ECCP1

PIC18F4480/4580 (40/44-pin) devices. The operation

of this feature is discussed in detail in Section 17.4.7

“Enhanced PWM Auto-Shutdown”.

Auto-shutdown features are not available for CCP1.

16.4.4

SETUP FOR PWM OPERATION

The following steps should be taken when configuring

the CCP module for PWM operation:

Set the PWM period by writing to the PR2

Set the PWM duty cycle by writing to the

CCPR1L register and CCP1CON<5:4> bits.

Make the CCP1 pin an output by clearing the

appropriate TRIS bit.

Set the TMR2 prescale value, then enable

Timer2 by writing to T2CON.

Configure the CCP1 module for PWM operation.

Note:

If the PWM duty cycle value is longer than

the PWM period, the CCP1 pin will not be

cleared.

PWM Resolution (max) =

FOSC

FPWM

log

log(2)

bits

⎛

⎝

⎞

⎠

PWM Frequency

2.44 kHz

9.77 kHz

39.06 kHz

156.25 kHz

312.50 kHz

416.67 kHz

Timer Prescaler (1, 4, 16)

41111

PR2 Value

FFh

3Fh

1Fh

17h

Maximum Resolution (bits)

6.58

PIC18F4580-E/ML Datasheet(PDF) 174 Page - Microchip Technology

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