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STA015 Datasheet(PDF) 22 Page - STMicroelectronics

Part # STA015
Description  MPEG 2.5 LAYER III AUDIO DECODER WITH ADPCM CAPABILITY
PDF  56 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA015 Datasheet(HTML) 22 Page - STMicroelectronics

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CMD_INTERRUPT
Address: 0x16 (22)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
X = don’t care;
0 = normal operation;
1 = write into I2C/Ancillary Data
The INTERRUPT is used to give STA015 the command to write into the I2C/Ancillary Data Buffer (Regis-
ters: 0x7E ... 0xB5). Every time the Master has to extract the new buffer content it writes into this register,
setting it to a non-zero value.
DATA_REQ_ENABLE
Address: 0x18 (24)
Type: R/W
Software Reset: 0x00
Hardware Reset: 0x00
The DATA_REQ_ENABLE register is used to configure Pin n. 28 working as buffered output clock or data
request signal, used for multimedia mode.
The buffered Output Clock has the same frequency than the input clock (XTI)
SYNCSTATUS
Address: 0x40 (64)
Type: RO
Software Reset: 0x00
Hardware Reset: 0x00
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
X
XXXX
XX
0
1
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
Description
XXXX
X
0
X
X
buffered output clock
XXXX
X
1
X
X
request signal
MSB
LSB
b7
b6
b5
b4
b3
b2
b1
b0
Description
XXXX
XX
SS1
SS0
0
0
Research of sync word
0
1
Wait for Confirmation
1
0
Synchronised



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