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PC312XDP512F0CFVR Datasheet(PDF) 983 Page - Freescale Semiconductor, Inc |
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PC312XDP512F0CFVR Datasheet(HTML) 983 Page - Freescale Semiconductor, Inc |
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983 / 1348 page  24.0.5 Register Descriptions Table 24-3 summarizes the effect on the various configuration bits, data direction (DDR), output level (IO), reduced drive (RDR), pull enable (PE), pull select (PS), and interrupt enable (IE) for the ports. The configuration bit PS is used for two purposes: 1. Configure the sensitive interrupt edge (rising or falling), if interrupt is enabled. 2. Select either a pull-up or pull-down device if PE is active. 0x0267 Port H Interrupt Flag Register (PIFH) Read / Write 0x0268 Port J Data Register (PTJ) Read / Write1 0x0269 Port J Input Register (PTIJ) Read 0x026A Port J Data Direction Register (DDRJ) Read / Write1 0x026B Port J Reduced Drive Register (RDRJ) Read / Write1 0x026C Port J Pull Device Enable Register (PERJ) Read / Write1 0x026D Port J Polarity Select Register (PPSJ) Read / Write1 0x026E Port J Interrupt Enable Register (PIEJ) Read / Write1 0x026F Port J Interrupt Flag Register (PIFJ) Read / Write1 0x0270 : 0x0277 PIM Reserved — 0x0278 Port AD1 Data Register 0 (PT0AD1) Read / Write 0x0279 Port AD1 Data Register 1 (PT1AD1) Read / Write 0x027A Port AD1 Data Direction Register 0 (DDR0AD1) Read / Write 0x027B Port AD1 Data Direction Register 1 (DDR1AD1) Read / Write 0x027C Port AD1 Reduced Drive Register 0 (RDR0AD1) Read / Write 0x027D Port AD1 Reduced Drive Register 1 (RDR1AD1) Read / Write 0x027E Port AD1 Pull Up Enable Register 0 (PER0AD1) Read / Write 0x027F Port AD1 Pull Up Enable Register 1 (PER1AD1) Read / Write 1. Write access not applicable for one or more register bits. Refer to Section 24.0.5, “Regis- ter Descriptions”. Table 24-2. PIM Memory Map (Sheet 3 of 3) Address Use Access |
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