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PC312XDP512F0CFVR Datasheet(PDF) 984 Page - Freescale Semiconductor, Inc |
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PC312XDP512F0CFVR Datasheet(HTML) 984 Page - Freescale Semiconductor, Inc |
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984 / 1348 page  Chapter 24 DG128 Port Integration Module (S12XDG128PIMV2) MC9S12XDP512 Data Sheet, Rev. 2.21 986 Freescale Semiconductor NOTE All register bits in this module are completely synchronous to internal clocks during a register read. Table 24-3. Pin Configuration Summary DDR IO RDR PE PS1 1. Always “0” on Port A, B, C, D, E, K, AD0, and AD1. IE2 2. Applicable only on Port P, H, and J. Function Pull Device Interrupt 0 x x 0 x 0 Input Disabled Disabled 0 x x 1 0 0 Input Pull Up Disabled 0 x x 1 1 0 Input Pull Down Disabled 0 x x 0 0 1 Input Disabled Falling edge 0 x x 0 1 1 Input Disabled Rising edge 0 x x 1 0 1 Input Pull Up Falling edge 0 x x 1 1 1 Input Pull Down Rising edge 1 0 0 x x 0 Output, full drive to 0 Disabled Disabled 1 1 0 x x 0 Output, full drive to 1 Disabled Disabled 1 0 1 x x 0 Output, reduced drive to 0 Disabled Disabled 1 1 1 x x 0 Output, reduced drive to 1 Disabled Disabled 1 0 0 x 0 1 Output, full drive to 0 Disabled Falling edge 1 1 0 x 1 1 Output, full drive to 1 Disabled Rising edge 1 0 1 x 0 1 Output, reduced drive to 0 Disabled Falling edge 1 1 1 x 1 1 Output, reduced drive to 1 Disabled Rising edge Register Name Bit 7 6 5 4 3 2 1 Bit 0 PORTA R PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 W PORTB R PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 W DDRA R DDRA7 DDRA6 DDRA5 DDRA4 DDRA3 DDRA2 DDRA1 DDRA0 W DDRB R DDRB7 DDRB6 DDRB5 DDRB4 DDRB3 DDRB2 DDRB1 DDRB0 W = Unimplemented or Reserved Figure 24-2. PIM Register Summary (Sheet 1 of 7) |
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