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PC912XDP512F0CALR Datasheet(PDF) 258 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0CALR Datasheet(HTML) 258 Page - Freescale Semiconductor, Inc |
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258 / 1348 page  Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.21 258 Freescale Semiconductor Operation M[RB, #OFFS5 ⇒ RD.L; $00 ⇒ RD.H M[RB, RI ] ⇒ RD.L; $00 ⇒ RD.H M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H; RI+1 ⇒ RI;1 RI-1 ⇒ RI; M[RS, RI] ⇒ RD.L; $00 ⇒ RD.H Loads a byte from memory into the low byte of register RD. The high byte is cleared. CCR Effects Code and CPU Cycles LDB Load Byte from Memory (Low Byte) LDB 1.If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not be incremented after the data move: M[RB, RI] ⇒ RD.L; $00 ⇒ RD.H NZ V C ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles LDB RD, (RB, #OFFS5) IDO5 0 1 0 0 0 RD RB OFFS5 Pr LDB RD, (RS, RI) IDR 0 1 1 0 0 RD RB RI 0 0 Pr LDB RD, (RS, RI+) IDR+ 0 1 1 0 0 RD RB RI 0 1 Pr LDB RD, (RS, -RI) -IDR 0 1 1 0 0 RD RB RI 1 0 Pr |
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