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PC912XDP512F0CALR Datasheet(PDF) 261 Page - Freescale Semiconductor, Inc |
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PC912XDP512F0CALR Datasheet(HTML) 261 Page - Freescale Semiconductor, Inc |
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261 / 1348 page  Chapter 6 XGATE (S12XGATEV2) MC9S12XDP512 Data Sheet, Rev. 2.21 Freescale Semiconductor 261 Operation M[RB, #OFFS5 ] ⇒ RD M[RB, RI ] ⇒ RD M[RB, RI] ⇒ RD; RI+2 ⇒ RI1 RI-2 ⇒ RI; M[RS, RI] ⇒ RD IMM16 ⇒ RD (translates to LDL RD, #IMM16[7:0]; LDH RD, #IMM16[15:8]) Loads a 16 bit value into the register RD. CCR Effects Code and CPU Cycles LDW Load Word from Memory LDW 1. If the same general purpose register is used as index (RI) and destination register (RD), the content of the register will not be incremented after the data move: M[RB, RI] ⇒ RD NZ V C ———— N: Not affected. Z: Not affected. V: Not affected. C: Not affected. Source Form Address Mode Machine Code Cycles LDW RD, (RB, #OFFS5) IDO5 0 1 0 0 1 RD RB OFFS5 PR LDW RD, (RB, RI) IDR 0 1 1 0 1 RD RB RI 0 0 PR LDW RD, (RB, RI+) IDR+ 0 1 1 0 1 RD RB RI 0 1 PR LDW RD, (RB, -RI) -IDR 0 1 1 0 1 RD RB RI 1 0 PR LDW RD, #IMM16 IMM8 1 1 1 1 0 RD IMM16[7:0] P IMM8 1 1 1 1 1 RD IMM16[15:8] P |
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