CDCE925PWR datasheet(21/27 Pages) TI

21 / 27 page

OUT +

Pdiv

VCO + ƒIN

log

[if P t 0 then P + 0]

CDCE925

CDCEL925

www.ti.com

SCAS847F – JULY 2007 – REVISED MARCH 2010

PLL Multiplier/Divider Definition

At a given input frequency (ƒIN), the output frequency (ƒOUT) of the CDCE925/CDCEL925 can be calculated:

(1)

where

M (1 to 511) and N (1 to 4095) are the multiplier/divide values of the PLL; Pdiv (1 to 127) is the output

divider.

The target VCO frequency (ƒVCO) of each PLL can be calculated:

(2)

The PLL internally operates as fractional divider and needs the following multiplier/divider settings:

NP = 4 – int

Q = int

R = N

′ – M × Q

where

′ = N × 2PN ≥ M100 MHz < ƒVCO > 200 MHz

≤ q ≤63

≤ p ≤ 7

≤ r ≤ 511

Example:

for ƒIN = 27 MHz; M = 1; N = 4; Pdiv = 2;

for ƒIN = 27 MHz; M = 2; N = 11; Pdiv = 2;

→ fOUT = 54 MHz

→ fOUT = 74.25 MHz

→ fVCO = 108 MHz

→ fVCO = 148.50 MHz

→ P = 4 – int(log24) = 4 – 2 = 2

→ P = 4 – int(log25.5) = 4 – 2 = 2

→ N′’ = 4 × 22 = 16

→ N′’ = 11 × 22 = 44

→ Q = int(16) = 16

→ Q = int(22) = 22

→ R = 16 – 16 = 0

→ R = 44 – 44 = 0

The values for P, Q, R, and N’ is automatically calculated when using TI Pro-Clock™ software.

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Product Folder Link(s): CDCE925 CDCEL925

CDCE925PWR Datasheet(PDF) 21 Page - Texas Instruments

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