NCP5392 datasheet(21/32 Pages) ONSEMI

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NCP5392

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PWM Comparators with Hysteresis

Four PWM comparators receive an error signal at their

noninverting input. Each comparator receives one of the

triangle waves at its inverting output. The output of each

comparator generates the PWM outputs G1, G2, G3, and

G4.

During steady state operation, the duty cycle will center

on the valley of the triangle waveform, with steady state

duty cycle calculated by Vout/Vin. During a transient event,

both high and low comparator output transitions shift phase

to the points where the error signal intersects the down and

up ramp of the triangle wave.

PROTECTION FEATURES

Undervoltage Lockout (VCC and 12VMON)

An undervoltage lockout (UVLO) senses the VCC input

directly. 12 V UVLO senses the 12 V power supply by

connecting it to the 12VMON pin through an appropriate

resistor divider. During power−up, both the VCC input and

12VMON are monitored, and the PWM outputs and the

soft−start circuit are disabled until both input voltages

exceed the threshold voltages of their individual UVLO

comparators. The UVLO comparators both incorporate

hysteresis to avoid chattering.

Overcurrent Shutdown

A programmable overcurrent function is incorporated

within the IC. A comparator and latch make up this

function. The inverting input of the comparator is

connected to the ILIM pin. The voltage at this pin sets the

maximum output current the converter can produce. The

ROSC pin provides a convenient and accurate reference

voltage from which a resistor divider can create the

overcurrent setpoint voltage. Although not actually

disabled, tying the ILIM pin directly to the ROSC pin sets

the limit above useful levels − effectively disabling

overcurrent shutdown. The comparator noninverting input

is the summed current information from the VDRP minus

offset voltage. The overcurrent latch is set when the current

information exceeds the voltage at the ILIM pin. The

outputs are pulled low, and the soft−start is pulled low. The

outputs will remain disabled until the VCC voltage is

removed and re−applied, or the ENABLE input is brought

low and then high.

Output Overvoltage and Undervoltage Protection and

Power Good Monitor

An output voltage monitor is incorporated. During

normal operation, if the output voltage is 180 mV (typical)

over the DAC voltage, the VR_RDY goes low, the DRVON

signal remains high, the PWM outputs are set low. The

outputs will remain disabled until the VCC voltage is

removed and reapplied. During normal operation, if the

output voltage falls more than 350 mV below the DAC

setting, the VR_RDY pin will be set low until the output

voltage rises.

Soft−Start

There are two possible soft−start modes: AMD and

VR11. AMD mode simply ramps Vcore from 0 V directly

to the DAC setting at a fixed rate. The VR11 mode ramps

Vcore to 1.1 V boot voltage at a fixed rate of 0.8 mV/mS,

pauses at 1.1 V for around 500

mS, reads the VID pins to

determine the DAC setting. Then ramps Vcore to the final

DAC setting at the Dynamic VID slew rate of up to

12.5 mV/

mS. Typical AMD and VR11 soft−start sequences

are shown in the following graphs (Figure 9 and 10).

APPLICATION INFORMATION

The NCP5392 demo board for the NCP5392 is available

by request. It is configured as a four phase solution with

decoupling designed to provide a 1 m

W load line under a

100 A step load.

Startup Procedure

Start by installing the test tool software. It is best to

power the test tool from a separate ATX power supply. The

test tool should be set to a valid VID code of 0.5 V or above

in order for the controller to start. Consult the VTT help

manual for more detailed instruction.

Step Load Testing

The VTT tool is used to generate the di/dt step load.

Select the dynamic loading option in the VTT test tool

software. Set the desired step load size, frequency, duty,

and slew rate. See Figure 6.

Figure 6. Typical Load Step Response

(full load, 35 A − 100 A)

Dynamic VID Testing

The VTT tool provides for VID stepping based on the

Intel Requirements. Select the Dynamic VID option.

Before enabling the test set the lowest VID to 0.5 V or

greater and set the highest VID to a value that is greater than

the lowest VID selection, then enable the test. See Figures

7 and 8.

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