MC68SC302 PRODUCT INFORMATION

— Memory Mode Accesses Supported (I/O Not Supported)

— Supports 8- or 16-bit Memory Cycles

— Supports Ring Detect through Status Change Pin

— Additional Chip Select Allows Another Device to be Address Mapped on the PC Card Bus.

• ISDN Communications Processor

— Requires No External (Local) RAM

— Flexible Channel Handling

— RISC Processor Decreases CPU Load with Flexible Buffer Descriptor Structure and HDLC

Capability (UART Mode Not Supported).

— Totally Independent Programming for Rx/Tx for each of the B and D Channels

— Supports Any Sub-Channeling for Each of the B Channels

— Enables a Concatenation of 2 B Channels (or Any Selected Bits) to a Super-Channel

— HDLC with Retry Capability for the D Channel

— Allows Dynamic Connection/Disconnection for each of the B Channels

— Total 1536KB Dual Port RAM Divided into Parameter and Data Buffer RAM

— 256 Byte Parameter RAM (As in PM302)

— 1280 Byte Data RAM with Efficient FIFO Organization and Flexible Buffer Size

— Independent Programmable Channel FIFO Length, if Split Equally:

• 4 x 256 Bytes FIFO for B1 and B2 Channel (Rx/Tx)

• 2 x 64 Bytes FIFO for D Channel (Rx/Tx)

— Glueless Interface to Freescale and Other Popular ISDN S/T and U Interface Chips

— Supports Freescale Interchip Digital Link (IDL)

— Includes Serial Communication Port (SCP) for Synchronous Communication

— Includes one SMC That Can Support Both the C/I and Monitor Channel of GCI

— Two Strobes Support Time-Slot Assignment of Non-Intelligent Peripherals

— Only One Crystal Required for TA Application.

— Clock Output (CLKO) Generation from a Crystal. CLKO Can Be Connected to S/T XTAL Input.

— Clock Input for U-Chip (MC145572) can be Used to Drive SC302

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com