11-107
RF2909
Rev B1 010904
11
Pin
Function
Description
Interface Schematic
19
RF OUT
Power Amp output, open collector output.
20
GND5
Same as pin 17.
21
GND6
Same as pin 17.
22
NC
23
I REF
Reference voltage for the I mixer. This voltage should be the same as
the DC voltage supplied to the I SIG pin. To obtain a carrier suppres-
sion of better than 25dB it may be tuned ±0.15V (relative to the I SIG
DC voltage). Without tuning, the carrier suppression will typically be
better than 25dB. The input impedance of this pin is 3k
Ω.
24
I SIG
Baseband input to the I mixer. A DC bias of approximately 1.7V is
present at this pin.A DC blocking capacitor is needed if the signal has a
different DC level. Maximum output power is obtained when the input
signal has a peak to peak amplitude of 1V. The input impedance of this
pin is about 3 k
Ω. The REF and SIG inputs are interchangeable. If
swapping the I SIG and I REF pins, the Q SIG and Q REF also need to
be swapped to maintain the correct phase. The SIG and REF pins may
be driven differentially to increase conversion gain.
See pin 23.
Table I
Operation
Mode
TX
PD
PLL
ON
PC 1
PC 2
APC
Function
Sleep Mode
Low
Low
Low
Low
0V
Entire chip is powered down. Total Icc<1µA.
PLL Buffer
Low
High
Low
Low
0V
LO Buffer is on. Icc=1.5mA
Linear Po Mode
High
High
Low
Low
0-VccV
Transmitter in on. Power output is proportional to APC.
Digital Po Mode
High
High
Low
Low
0V
Transmitter is on. Power out is 1mW.
Medium Power
High
High
High
Low
0V
Transmitter is on. Power out is 10mW.
High Power
High
High
Low
High
0V
Transmitter is on. Power out is 70mW.
RF OUT
INSTGT
BIAS
I REF
I SIG
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