KM416RD8ACD-RK80 datasheet(35/64 Pages) SAMSUNG

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Page 32

KM416RD8AC(D)/KM418RD8AC(D)

Direct RDRAM™

Rev. 1.01 Oct. 1999

Figure 27: INIT Register

Figure 28: CNFGA Register

15 14 13 12 11 10

SDE

VID

TSQ

DIS

TEN LSR

NSR

PSR

SRP PSX

Control Register: INIT

Read/write register.

Reset values are undefined except as affected by SIO Reset as noted

below. SETR/CLRR Reset does not affect this register.

SDEVID5..0 - Serial Device Identification. Compared to SDEV5..0

serial address field of serial request packet for register read/write transac-

tions. This determines which RDRAM is selected for the register read or

write operation. SDEVID resets to 3f16.

PSX - Power Exit Select. PDN and NAP are exited with (=0) or without (=1) a device address on the

DQA5..0 pins. PDEV5 (on DQA5) selectes broadcast (1) or directed (0) exit. For a directed exit,

PDEV4..0 (on DQA4..0) is compared to DEVID4..0 to select a device.

SRP - SIO Repeater. Controls value on SIO1; SIO1=SIO0 if SRP=1, SIO1=1 if SRP=0. SRP resets

to 1.

NAP Self-Refresh. NSR=1 enables self-refresh in NAP mode. NSR can’t be set while in NAP mode.

NSR resets to 0.

PDN Self-Refresh. PSR=1 enables self-refresh in PDN mode. PSR can’t be set while in PDN mode.

PSR resets to 0.

Low Power Self-Refresh. LSR=1 enables longer self-refresh interval. The self-refresh supply

current is reduced. LSR resets to 0.

Temperature Sensing Enable. TEN=1 enables temperature sensing circuitry, permitting the TSQ bit

to be read to determine if a thermal trip point has been exceeded. TEN resets to 0.

Temperature Sensing Output. TSQ=1 when a temperature trip point has been exceeded, TSQ=0

when it has not. TSQ is available during a current control operation (see Figure 51).

RDRAM Disable. DIS=1 causes RDRAM to ignore NAP/PDN exit sequence, DIS=0 permits

Address: 02116

SDEVID4..SDEVID0

15 14 13 12 11 10

DBL

MVER5..0

= 010000

PVER5..0

= 000001

Control Register: CNFGA

Address: 02316

Read-only register.

REFBIT2..0 - Refresh Bank Bits. Specifies the number of

bank address bits used by REFA and REFP commands.

Permits multi-bank refresh in future RDRAMs.

DBL - Doubled-Bank. DBL=1 means the device uses a

doubled-bank architecture with adjacent-bank dependency.

DBL=0 means no dependency.

MVER5..0 - Manufacturer Version. Specifies the manufac-

turer identification number.

PVER5..0 - Protocol Version. Specifies the Direct Protocol

version used by this device:

0 - Compliant with version 0.62.

1 - Compliant with version 0.7 through this version.

2 to 63 - Reserved.

Note: In RDRAMs with protocol version 1 PVER[5:0] = 000001, the

range of the PDNX field (PDNX[2:0] in the PDNX register) may not

be large enough to specify the location of the restricted interval in

Figure 47. In this case, the effective tS4 parameter must increase and

no row or column packets may overlap the restricted interval. See

Figure 47 and Table 19.

REFBIT2..0

= 101

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