K6R1016V1D

CMOS SRAM

Revision 3.0

- 5 -

June 2002

for AT&T

TEST CONDITIONS*

* The above test conditions are also applied at industrial temperature range.

Parameter

Value

Input Pulse Levels

0V to 3V

Input Rise and Fall Times

3ns

Input and Output timing Reference Levels

1.5V

Output Loads

See below

°C, Vcc=3.3V+0.3V/-0.15V, unless otherwise noted.)

Output Loads(B)

5pF*

319

Ω

353

Ω

+3.3V

* Including Scope and Jig Capacitance

Output Loads(A)

Ω

Ω

30pF*

* Capacitive Load consists of all components of the

test environment.

°C, f=1.0MHz)

* Capacitance is sampled and not 100% tested.

Item

Symbol

Test Conditions

MIN

Max

Unit

Input/Output Capacitance

-

8

pF

Input Capacitance

-

6

pF

°C, Vcc=3.3±0.3V, unless otherwise specified)

* The above parameters are also guaranteed at industrial temperature range.

Parameter

Symbol

Test Conditions

Min

Max

Unit

Input Leakage Current

-2

2

µA

Output Leakage Current

-2

2

µA

Operating Current

Min. Cycle, 100% Duty

Com.

8ns

-

80

mA

10ns

-

65

Ind.

8ns

-

90

10ns

-

75

Standby Current

-

20

mA

f=0MHz, CS

-

5

Output Low Voltage Level

-

0.4

V

Output High Voltage Level

2.4

-

V