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© 2009 Semtech Corp.

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SC2596

PRELIMINARY

POWER MANAGEMENT

Application Information (Cont.)

Application_2: Lower Power Loss Configuration for

SSTL-2

If power loss is a major concern, separating the PVCC

form AVCC and VDDQ will be a good choice (Figure 2).

The PVCC can operate at lower voltage (1.8V to 2.5V) if

2.5V voltage is applied on AVCC and the VDDQ, the source

current is lower due to the lower operating voltage ap-

plied on the PVCC.

Figure 2: Lower power loss for SSTL-2(DDR-I).

Application_4: High Source Current Configuration

If there is a need for VTT to source more current, espe-

cially for DDR-II applications, the system designer can tie

the AVCC and PVCC to 3.3V while has the VDDQ tie to

1.8V. This configuration can ensure more than 2A source

and sink capability from the VTT rail.

Notes:

(a) The preferred configuration for DDR-I applications is to tie AVCC and PVCC to VDDQ, which is typically 2.5V.

(b) If AVCC and PVCC rails are tied together, then the VDDQ cannot lead the AVCC and PVCC.

Figure 3: Lower power loss for SSTL-18(DDR-II).

VREF/0.9V

0

AVCC/PVCC=3.3V

VDDQ=1.8V

VTT/0.9V

EN

CIN2

100uF

CIN2

100uF

COUT

220uF

COUT

220uF

CIN1

1uF

CIN1

1uF

CREF

100nF

CREF

100nF

1M

1M

Csense

100nF

Csense

100nF

COUT

10uF

COUT

10uF

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GND

1

EN

2

VSENSE

3

VREF

4

VDDQ

5

AVCC

6

PVCC

7

VTT

8

VREF/1.25V

0

PVCC=2.5V

VDDQ/AVCC=2.5V

VTT/1.25V

EN/2.5V

CIN2

100uF

CIN2

100uF

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GND

1

EN

2

VSENSE

3

VREF

4

VDDQ

5

AVCC

6

PVCC

7

VTT

8

CIN1

1uF

CIN1

1uF

1M

1M

Csense

100nF

Csense

100nF

COUT

220uF

COUT

220uF

CREF

100nF

CREF

100nF

Application_3: Low Power Loss Configuration for

SSTL-18(DDR-II)

If power loss is a major concern, setting the PVCC to be

2.5V will be a good choice (Figure 3). The PVCC can op-

erate at lower voltage. if 2.5V voltage is applied on AVCC

and PVCC, the source current is lower due to the lower

operating voltage applied on the PVCC.

VREF/0.9V

0

AVCC/PVCC=2.5V

VDDQ=1.8V

VTT/0.9V

EN

CREF

100nF

CREF

100nF

COUT

220uF

COUT

220uF

CIN2

100uF

CIN2

100uF

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GND

1

EN

2

VSENSE

3

VREF

4

VDDQ

5

AVCC

6

PVCC

7

VTT

8

Csense

100nF

Csense

100nF

1M

1M

CIN1

1uF

CIN1

1uF

Figure 4: High current set up for SSTL-18(DDR-II).

Application_5: All Ceramic Capacitor Configuration

Figure 5: All ceramic capacitor configuration.

For some pure ceramic output capacitor designs, one

needs to add small ESR in series with the output capaci-

tor in order to enhance stability margin. For example, an

100mohm external ESR is suggested to help improve

the phase margin for the circuit in Figure 5. Figure 6

shows the corresponding Bode plot.

EN

VTT/0.9V

VREF/0.9V

0

AVCC=3.3V

VDDQ/PVCC=1.8V

External R

100mOhm

External R

100mOhm

Csense

100nF

Csense

100nF

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GND

1

EN

2

VSENSE

3

VREF

4

VDDQ

5

AVCC

6

PVCC

7

VTT

8

1M

1M

COUT

10uF

COUT

10uF

CREF

100nF

CREF

100nF

CIN3

10uF

CIN3

10uF

CIN2

1uF

CIN2

1uF

CIN1

1uF

CIN1

1uF