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AD9650-65EBZ Datasheet(PDF) 7 Page - Analog Devices

Part # AD9650-65EBZ
Description  16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC)
PDF  44 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD9650-65EBZ Datasheet(HTML) 7 Page - Analog Devices

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AD9650
Rev. 0 | Page 7 of 44
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, maximum sample rate, VIN = −1.0 dBFS differential input, 1.35 V internal reference, and DCS enabled,
unless otherwise noted.
Table 4.
AD9650BCPZ-25
AD9650BCPZ-65
AD9650BCPZ-80
AD9650BCPZ-105
Parameter
Temp
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Unit
CLOCK INPUT PARAMETERS
Input Clock Rate
Full
200
520
640
640
MHz
Conversion Rate1
DCS Enabled
Full
20
25
20
65
20
80
20
105
MSPS
DCS Disabled
Full
10
25
10
65
10
80
10
105
MSPS
CLK Period—Divide-by-1
Mode (tCLK)
Full
40
15.4
12.5
9.5
ns
CLK Pulse Width High (tCH)
Divide-by-1 Mode, DCS
Enabled
Full
12
20
28
4.65
7.70
10.75
3.75
6.25
8.75
2.85
4.75
6.65
ns
Divide-by-1 Mode, DCS
Disabled
Full
19
20
21
7.33
7.70
8.07
5.95
6.25
6.55
4.5
4.75
5.0
ns
Divide-by-2 Mode
Through Divide-by-8
Mode
Full
0.8
0.8
0.8
0.8
ns
Aperture Delay (tA)
Full
1.0
1.0
1.0
1.0
ns
Aperture Uncertainty
(Jitter, tJ)
Full
0.100
0.090
0.080
0.075
ps rms
DATA OUTPUT PARAMETERS
CMOS Mode
Data Propagation Delay
(tPD)
Full
2.8
3.5
4.2
2.8
3.5
4.2
2.8
3.5
4.2
2.8
3.5
4.2
ns
DCO Propagation Delay
(tDCO)2
Full
3.1
3.1
3.1
3.1
ns
DCO to Data Skew (tSKEW)
Full
−0.6
−0.4
0
−0.6
−0.4
0
−0.6
−0.4
0
−0.6
−0.4
0
ns
LVDS Mode
Data Propagation Delay
(tPD)
Full
2.9
3.7
4.5
2.9
3.7
4.5
2.9
3.7
4.5
2.9
3.7
4.5
ns
DCO Propagation Delay
(tDCO)2
Full
3.9
3.9
3.9
3.9
ns
DCO to Data Skew (tSKEW)
Full
−0.1
+0.2
+0.5
−0.1
+0.2
+0.5
−0.1
+0.2
+0.5
−0.1
+0.2
+0.5
ns
CMOS Mode Pipeline Delay
(Latency)
Full
12
12
12
12
Cycles
LVDS Mode Pipeline Delay
(Latency) Channel A/
Channel B
Full
12/12.5
12/12.5
12/12.5
12/12.5
Cycles
Wake-Up Time3
Full
500
500
500
500
μs
Out-of-Range Recovery
Time
Full
2
2
2
2
Cycles
1 Conversion rate is the clock rate after the divider.
2 Additional DCO delay can be added by writing to Bit 0 through Bit 4 in SPI Register 0x17 (see
).
Table 17
3 Wake-up time is defined as the time required to return to normal operation from power-down mode.



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