ADUC7124 datasheet(21/96 Pages) AD

21 / 96 page

ADuC7124

Rev. 0 | Page 21 of 96

More information relative to the model of the programmer and

the ARM7TDMI core architecture can be found in the following

materials from ARM:

•

DDI0029G, ARM7TDMI Technical Reference Manual

•

DDI-0100, ARM Architecture Reference Manual

INTERRUPT LATENCY

The worst-case latency for a fast interrupt request (FIQ) consists

of the following:

•

The longest time the request can take to pass through the

synchronizer

•

The time for the longest instruction to complete (the longest

instruction is an LDM) that loads all the registers including

the PC

•

The time for the data abort entry

•

The time for the FIQ entry

At the end of this time, the ARM7TDMI executes the instruction

at 0x1C (FIQ interrupt vector address). The maximum total time

is 50 processor cycles, which is just under 1.2 µs in a system using

a continuous 41.78 MHz processor clock.

The maximum interrupt request (IRQ) latency calculation is

similar but must allow for the fact that FIQ has higher priority

and could delay entry into the IRQ handling routine for an

arbitrary length of time. This time can be reduced to 42 cycles if

the LDM command is not used. Some compilers have an option

to compile without using this command. Another option is to run the

part in Thumb mode where the time is reduced to 22 cycles.

The minimum latency for FIQ or IRQ interrupts is a total of five

cycles, which consist of the shortest time the request can take through

the synchronizer plus the time to enter the exception mode.

Note that the ARM7TDMI always runs in ARM (32-bit) mode

when in privileged modes, for example, when executing interrupt

service routines.

ADUC7124 Datasheet(PDF) 21 Page - Analog Devices