MCP3901 datasheet(39/60 Pages) MICROCHIP

39 / 60 page

DS22192C-page 39

MCP3901

The position of the DR pulses vary, with respect to this

mode, to the OSR and to the PHASE settings:

• DRMODE<1:0> = 11: Both data ready pulses

from ADC Channel 0 and ADC Channel 1 are

output on the DR pin.

• DRMODE<1:0> = 10: Data ready pulses from

ADC Channel 1 are output on the DR pin. The DR

from ADC Channel 0 is not present on the pin.

• DRMODE<1:0> = 01: Data ready pulses from

ADC Channel 0 are output on the DR pin. The DR

from ADC Channel 1 is not present on the pin.

• DRMODE<1:0> = 00 (Recommended and

Default mode): Data ready pulses from the

lagging ADC between the two are output on the

DR pin. The lagging ADC depends on the PHASE

ADCs are linked together so their data is latched

together when the lagging ADC output is ready.

6.10.2

DR PULSES WITH SHUTDOWN OR

RESET CONDITIONS

There will be no DR pulses if DRMODE<1:0> = 00

when either one or both of the ADCs are in Reset or

shutdown. In Mode 0,0, a DR pulse only happens when

both ADCs are ready. Any DR pulse will correspond to

one data on both ADCs. The two ADCs are linked

together and act as if there was only one channel with

the combined data of both ADCs. This mode is very

practical when both ADC channels’ data retrieval and

processing need to be synchronized, as in power

metering applications.

Figure 6-8 represents the behavior of the data ready

with

the

different

DRMODE

and

DR_LTY

configurations, while shutdown or Resets are applied.

Note:

If DRMODE<1:0> = 11, the user will still

be able to retrieve the DR pulse for the

ADC not in shutdown or Reset (i.e., only

1 ADC channel needs to be awake).

MCP3901 Datasheet(PDF) 39 Page - Microchip Technology

MCP3901 Datasheet(HTML) 39 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL