PIC18F23K22-ESLASHML datasheet(266/496 Pages) MICROCHIP

266 / 496 page

PIC18(L)F2X/4XK22

DS41412C-page 266

Preliminary

 2010 Microchip Technology Inc.

16.1.1.5

TSR Status

The TRMT bit of the TXSTAx register indicates the

status of the TSR register. This is a read-only bit. The

TRMT bit is set when the TSR register is empty and is

cleared when a character is transferred to the TSR

until all bits have been shifted out of the TSR register.

No interrupt logic is tied to this bit, so the user needs to

poll this bit to determine the TSR status.

16.1.1.6

Transmitting 9-Bit Characters

The EUSART supports 9-bit character transmissions.

When the TX9 bit of the TXSTAx register is set the

EUSART will shift 9 bits out for each character transmit-

ted. The TX9D bit of the TXSTAx register is the ninth,

and Most Significant, data bit. When transmitting 9-bit

data, the TX9D data bit must be written before writing

the 8 Least Significant bits into the TXREGx. All nine

bits of data will be transferred to the TSR shift register

immediately after the TXREGx is written.

A special 9-bit Address mode is available for use with

multiple receivers. See Section 16.1.2.8 “Address

Detection” for more information on the Address mode.

16.1.1.7

Asynchronous Transmission Set-up:

Initialize the SPBRGHx:SPBRGx register pair

and the BRGH and BRG16 bits to achieve the

desired baud rate (see Section 16.3 “EUSART

Baud Rate Generator (BRG)”).

Set the RXx/DTx and TXx/CKx TRIS controls to

‘1’.

Enable the asynchronous serial port by clearing

the SYNC bit and setting the SPEN bit.

If 9-bit transmission is desired, set the TX9 con-

trol bit. A set ninth data bit will indicate that the 8

Least Significant data bits are an address when

the receiver is set for address detection.

Set the CKTXP control bit if inverted transmit

data polarity is desired.

Enable the transmission by setting the TXEN

control bit. This will cause the TXxIF interrupt bit

to be set.

If interrupts are desired, set the TXxIE interrupt

enable bit. An interrupt will occur immediately

provided that the GIE/GIEH and PEIE/GIEL bits

of the INTCON register are also set.

If 9-bit transmission is selected, the ninth bit

should be loaded into the TX9D data bit.

Load 8-bit data into the TXREGx register. This

will start the transmission.

FIGURE 16-3:

ASYNCHRONOUS TRANSMISSION

Note:

The TSR register is not mapped in data

memory, so it is not available to the user.

Word 1

Stop bit

Word 1

Transmit Shift Reg

Start bit

bit 0

bit 1

bit 7/8

Write to TXREGx

Word 1

BRG Output

(Shift Clock)

TXx/CKx

TXxIF bit

(Transmit Buffer

Reg. Empty Flag)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

1 TCY

PIC18F23K22-E/ML Datasheet(PDF) 266 Page - Microchip Technology

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