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PIC18F23K22-E/ML Datasheet(PDF) 306 Page - Microchip Technology |
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PIC18F23K22-E/ML Datasheet(HTML) 306 Page - Microchip Technology |
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306 / 496 page ![]() PIC18(L)F2X/4XK22 DS41412C-page 306 Preliminary 2010 Microchip Technology Inc. FIGURE 18-2: COMPARATOR C1/C2 SIMPLIFIED BLOCK DIAGRAM Note 1: When C1ON = 0, the C1 comparator will produce a ‘0’ output to the XOR Gate. 2: Q1 and Q3 are phases of the four-phase system clock (FOSC). 3: Q1 is held high during Sleep mode. 4: Synchronized comparator output should not be used to gate Timer1 in conjunction with synchronized T1CKI. Cx CxPOL to PWM Logic 0 1 2 3 CxON(1) CxCH<1:0> 2 0 1 CxR CM2CON1 (MCxOUT) To Interrupts CxVIN - CxVIN + C12IN0- C12IN1- C12IN2- C12IN3- CxIN+ DQ EN Q1(2),(3) DQ EN CL Read or Write Reset + - 0 1 DAC CXRSEL FVR BUF1 CxSP CXVREF CxOE C xOUT Timer1 Clock DQ SYNCC xOUT To CMxCON0 (CxOUT) (CxIF) of CMxCON0 Q3(2) 0 1 CxSYNC C x Output TRIS bit - to SR Latch - to TxG MUX(4) |
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