PIC18F23K22-ESLASHML datasheet(368/496 Pages) MICROCHIP

368 / 496 page

PIC18(L)F2X/4XK22

DS41412C-page 368

Preliminary

 2010 Microchip Technology Inc.

TABLE 25-1:

OPCODE FIELD DESCRIPTIONS

Field

Description

RAM access bit

a = 0: RAM location in Access RAM (BSR register is ignored)

a = 1: RAM bank is specified by BSR register

bbb

Bit address within an 8-bit file register (0 to 7).

BSR

Bank Select Register. Used to select the current RAM bank.

C, DC, Z, OV, N

ALU Status bits: Carry, Digit Carry, Zero, Overflow, Negative.

Destination select bit

d = 0: store result in WREG

d = 1: store result in file register f

dest

Destination: either the WREG register or the specified register file location.

8-bit Register file address (00h to FFh) or 2-bit FSR designator (0h to 3h).

12-bit Register file address (000h to FFFh). This is the source address.

12-bit Register file address (000h to FFFh). This is the destination address.

GIE

Global Interrupt Enable bit.

Literal field, constant data or label (may be either an 8-bit, 12-bit or a 20-bit value).

label

Label name.

The mode of the TBLPTR register for the table read and table write instructions.

Only used with table read and table write instructions:

No change to register (such as TBLPTR with table reads and writes)

Post-Increment register (such as TBLPTR with table reads and writes)

Post-Decrement register (such as TBLPTR with table reads and writes)

Pre-Increment register (such as TBLPTR with table reads and writes)

The relative address (2’s complement number) for relative branch instructions or the direct address for

CALL/BRANCH and RETURN instructions.

Program Counter.

PCL

Program Counter Low Byte.

PCH

Program Counter High Byte.

PCLATH

Program Counter High Byte Latch.

PCLATU

Program Counter Upper Byte Latch.

Power-down bit.

PRODH

Product of Multiply High Byte.

PRODL

Product of Multiply Low Byte.

Fast Call/Return mode select bit

s = 0: do not update into/from shadow registers

s = 1: certain registers loaded into/from shadow registers (Fast mode)

TBLPTR

21-bit Table Pointer (points to a Program Memory location).

TABLAT

8-bit Table Latch.

Time-out bit.

TOS

Top-of-Stack.

Unused or unchanged.

WDT

Watchdog Timer.

WREG

Working register (accumulator).

Don’t care (‘0’ or ‘1’). The assembler will generate code with x = 0. It is the recommended form of use for

compatibility with all Microchip software tools.

7-bit offset value for indirect addressing of register files (source).

7-bit offset value for indirect addressing of register files (destination).

{

}

Optional argument.

[text]

Indicates an indexed address.

(text)

The contents of text.

[expr]<n>

Specifies bit n of the register indicated by the pointer expr.



Assigned to.

< >



In the set of.

italics

User defined term (font is Courier).

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