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Copyright © 2010 Future Technology Devices International Limited

12

Document Reference No.: FT_000198

MORPH-IC-II Datasheet

Version 1.02

Clearance No.: FTDI#

164

10

VCCUSB

AD4

AD6

TXE#

WR#

GND

IOK1

IOP11

3V3IO

IOT4

IOR3

GND

IOL4

IOP4

3V3IO

IOP5

IOR7

GND

NC

IOL9

VCCSW

AD5

AD7

RXF#

RD#

GND

RESETIN#

IOC1

3V3IO

IOT7

IOL3

GND

IOM4

IOK4

3V3IO

IOK5

ION8

GND

IOR8

IOM11

7

8

6

5

4

3

1

2

16

13

14

12

11

9

22

19

20

18

17

15

28

27

25

26

24

23

21

34

31

32

30

29

40

37

38

36

35

33

39

10

AD3

AD0

NC

IOE4

IOE5

GND

IOA7

IOA3

3V3IO

IOA5

IOA6

GND

IOG7

IOG6

V_BANK4

IOD5

IOE6

GND

IOF9

IOC12

AD2

AD1

NC

IOE3

IOD4

GND

CLKIN

GND

3V3IO

IOD6

IOB7

GND

IOA9

IOF6

V_BANK4

IOC5

IOD8

GND

IOC11

IOC13

7

8

6

5

4

3

1

2

16

13

14

12

11

9

22

19

20

18

17

15

28

27

25

26

24

23

21

34

31

32

30

29

40

37

38

36

35

33

39

Morph-IC II Pin-out

J1

(Top View)

Morph-IC II Pin-out

J2

(Top View)

Fixed Voltage

Lines

Variable Voltage

Lines

Fig. 4 – Pin outs of J1 & J2

# = Active Low

The signal names of J1 and J2 are illustrated in Fig. 4. The pins are colour coded to indicate whether or

not the pin is associated with I/O BANK4. Likewise Fig. 5 defines the pins associated with the variable

voltage level tolerant I/O BANK4. Fig 5 also details labelling of J3 and J4 signals.