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ADS1178IPAPR Datasheet(PDF) 23 Page - Texas Instruments

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Part # ADS1178IPAPR
Description  Quad/Octal, Simultaneous Sampling, 16-Bit Analog-to-Digital Converters
PDF  39 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADS1178IPAPR Datasheet(HTML) 23 Page - Texas Instruments

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POWER SUPPLIES
DRDY
(SPIProtocol)
DOUT
(Frame-SyncProtocol)
InternalReset
CLK
3Vnom
(1)
AVDD
1Vnom
(1)
IOVDD
1Vnom
(1)
DVDD
ValidData
2
18
f
CLK
129(max)
t
DATA
ADS1174
ADS1178
www.ti.com ........................................................................................................................................ SBAS373B – OCTOBER 2007 – REVISED SEPTEMBER 2008
be sequenced at the same time if the supplies are
tied together. Each supply has an internal reset circuit
The ADS1174/78 has three power supplies: AVDD,
whose outputs are summed together to generate a
DVDD, and IOVDD. AVDD is the analog supply that
global power-on reset. After the supplies have
powers the modulator, DVDD is the digital supply that
exceeded the reset thresholds, 218 fCLK cycles are
powers the digital core, and IOVDD is the digital I/O
counted before the converter initiates the conversion
power supply. The IOVDD and DVDD power supplies
process. Following the CLK cycles, the data for 129
can be tied together if desired (+1.8V). To achieve
conversions are suppressed by the ADS1174/78 to
rated performance, it is critical that the power
allow output of fully-settled data. In SPI protocol,
supplies
are
bypassed
with
0.1
µF and 10µF
DRDY is held high during this interval. In frame-sync
capacitors placed as close as possible to the supply
protocol, DOUT is forced to zero. The power supplies
pins. A single 10
µF ceramic capacitor may be
should be applied before any analog or digital pin is
substituted in place of the two capacitors.
driven. For consistent performance, assert SYNC
after device power-on when data first appear.
Figure 24 shows the start-up sequence of the
ADS1174/78. At power-on, bring up the DVDD supply
first, followed by IOVDD and then AVDD. Check the
power-supply sequence for proper order, including
the ramp rate of each supply. DVDD and IOVDD may
(1) The power-supply reset thresholds are approximate.
Figure 24. Start-Up Sequence
Copyright © 2007–2008, Texas Instruments Incorporated
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Product Folder Link(s): ADS1174 ADS1178



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