PIC18F8723 datasheet(39/60 Pages) MICROCHIP

39 / 60 page

Preliminary

DS39894A-page 37

PIC18F8723 FAMILY

2.6

A/D Conversions

Figure 2-4 shows the operation of the A/D Converter

after the GO/DONE bit has been set and the

ACQT2:ACQT0 bits are cleared. A conversion is

started after the following instruction to allow entry into

Sleep mode before the conversion begins.

Figure 2-5 shows the operation of the A/D Converter

after

the

GO/DONE

bit

has

been

set,

the

ACQT2:ACQT0 bits are set to ‘010’ and a 4 TAD acqui-

sition time has been selected before the conversion

starts.

Clearing the GO/DONE bit during a conversion will abort

the current conversion. The A/D Result register pair will

NOT be updated with the partially completed A/D

conversion sample. This means the ADRESH:ADRESL

registers will continue to contain the value of the last

completed conversion (or the last value written to the

ADRESH:ADRESL registers).

After the A/D conversion is completed or aborted, a

2TCY wait is required before the next acquisition can

be started. After this wait, acquisition on the selected

channel is automatically started.

2.7

Discharge

The discharge phase is used to initialize the value of

the holding capacitor. The array is discharged before

every sample. This feature helps to optimize the unity

gain amplifier, as the circuit always needs to charge the

capacitor array, rather than charge/discharge based on

previous measure values.

FIGURE 2-4:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 000, TACQ = 0)

FIGURE 2-5:

A/D CONVERSION TAD CYCLES (ACQT<2:0> = 010, TACQ = 4 TAD)

Note:

The GO/DONE bit should NOT be set in

the same instruction that turns on the A/D.

Code should wait at least 2

μs after

enabling the A/D before beginning an

acquisition and conversion cycle.

TAD1 TAD2 TAD3 TAD4 TAD5 TAD6 TAD7 TAD8

TAD11

Set GO/DONE bit

Holding capacitor is disconnected from analog input (typically 100 ns)

TAD9 TAD10

TCY – TAD

ADRESH:ADRESL are loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input

Conversion starts

b11

b10

On the following cycle:

Discharge

TAD13

TAD12

TAD1

(typically 200 ns)

Set GO/DONE bit

(Holding capacitor is disconnected)

Conversion starts

(Holding capacitor continues

acquiring input)

TACQT Cycles

TAD Cycles

Automatic

Acquisition

Time

b11

b10

ADRESH:ADRESL are loaded, GO/DONE bit is cleared,

ADIF bit is set, holding capacitor is connected to analog input

On the following cycle:

TAD1

Discharge

(typically

200 ns)

PIC18F8723 Datasheet(PDF) 39 Page - Microchip Technology

PIC18F8723 Datasheet(HTML) 39 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60

Datasheet Download

Link URL