82562V datasheet(21/42 Pages) INTEL

21 / 42 page

Networking Silicon — 82562V

Datasheet

6.1.2

Isolate

This bit allows the PHY to isolate the medium independent

interface. The PHY is disconnected from the LAN Connect

block on both the transmit and receive side.

0 =

Normal operation

1 =

Isolates internal medium independent interface

0RW

Restart Auto-

Negotiation

This bit restarts the Auto-Negotiation process and is self-

clearing.

0 =

Normal operation

1 =

Restart Auto-Negotiation process

0RW

Duplex Mode

This bit controls the duplex mode when Auto-Negotiation is

disabled. When Auto-Negotiation is enabled this bit is read

only and always equals 1b.

When the PHY is placed in Loopback mode, the behavior of

the PHY shall not be affected by the status of this bit.

0 =

Half Duplex

1 =

Full Duplex

0RW/

Collision Test

This bit is not used in the 82562V and has a default value of 1b.

(If it is used in other devices, it forces a collision in response to

the assertion of the transmit enable signal.)

1RW

6:0

Reserved

These bits are reserved and should be set to 0b.

Bit(s)

Name

Description

Default

R/W

Reserved

This bit is reserved and should be set to 0b.

100BASE-TX Full-

duplex

This bit enables 100BASE-TX full-duplex operation and is

dependent on ADV10. If ADV10 is active, the default

value is 0.

0 =

PHY unable to perform full-duplex 100BASE-TX

1 =

PHY able to perform full-duplex 100BASE-TX

1RO

100 Mbps Half-

duplex

This bit enables 100BASE-TX half-duplex operation and is

dependent on ADV10. If ADV10 is active, the default

value is 0.

0 =

PHY unable to perform half-duplex 100BASE-TX

1 =

PHY able to perform half-duplex 100BASE-TX

1RO

10 Mbps Full-

duplex

This bit enables 10BASE-T full duplex operation.

0 =

PHY unable to perform full-duplex 10BASE-T

1 =

PHY able to perform full-duplex 10BASE-T

1RO

10 Mbps Half-

duplex

This bit enables 10BASE-T half-duplex operation.

0 =

PHY unable to perform half-duplex 10BASE-T

1 =

PHY able to perform half-duplex 10BASE-T

1RO

10:7

Reserved

These bits are reserved and should be set to 0b.

Management

Frames Preamble

Suppression

This bit allows the 82562V to receive management frames

with suppressed preamble.

0 =

PHY will not accept management frames with

preamble suppressed

1 =

PHY will accept management frames with preamble

suppressed

0RO

Bit(s)

Name

Description

Default

R/W

82562V Datasheet(PDF) 21 Page - Intel Corporation

82562V Datasheet(HTML) 21 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42

Datasheet Download

Link URL