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PIC24FJ64GA Datasheet(PDF) 127 Page - Microchip Technology |
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PIC24FJ64GA Datasheet(HTML) 127 Page - Microchip Technology |
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127 / 262 page ![]() © 2008 Microchip Technology Inc. Preliminary DS39881C-page 125 PIC24FJ64GA004 FAMILY 12.0 INPUT CAPTURE FIGURE 12-1: INPUT CAPTURE BLOCK DIAGRAM Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 15. Input Capture” (DS39701). ICxBUF ICx Pin ICM<2:0> (ICxCON<2:0>) Mode Select 3 10 Set Flag ICxIF (in IFSn Register) TMRy TMRx Edge Detection Logic 16 16 FIFO R/W Logic ICI<1:0> ICOV, ICBNE (ICxCON<4:3>) ICxCON Interrupt Logic System Bus From 16-Bit Timers ICTMR (ICxCON<7>) Prescaler Counter (1, 4, 16) and Clock Synchronizer Note 1: An ‘x’ in a signal, register or bit name denotes the number of the capture channel. 2: This peripheral’s inputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information. |
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