Clock operations

M48T37Y, M48T37V

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Doc ID 7019 Rev 9

Two methods are available for ascertaining how much calibration a given M48T37Y/V may

require. The first involves simply setting the clock, letting it run for a month and comparing it

to a known accurate reference (like WWW broadcasts). While that may seem crude, it

allows the designer to give the end user the ability to calibrate his clock as his environment

may require, even after the final product is packaged in a non-user serviceable enclosure.

All the designer has to do is provide a simple utility that accesses the calibration byte.

The second approach is better suited to a manufacturing environment, and involves the use

of the IRQ/FT pin. The pin will toggle at 512 Hz when the stop bit (ST, D7 of 7FF9h) is '0' the

frequency test bit (FT, D6 of 7FFCh) is '1,' the alarm flag enable bit (AFE, D7 of 7FF6h) is '0,'

and the watchdog steering bit (WDS, D7 of 7FF7h) is '1' or the watchdog register is reset

(7FF7h=0).

Any deviation from 512 Hz indicates the degree and direction of oscillator frequency shift at

the test temperature. For example, a reading of 512.01024 Hz would indicate a +20 ppm

oscillator frequency error, requiring a –10(WR001010) to be loaded into the calibration byte

for correction.

Note:

Setting or changing the calibration byte does not affect the frequency test output frequency.

The IRQ/FT pin is an open drain output which requires a pull-up resistor for proper

operation. A 500-10 k

Ω resistor is recommended in order to control the rise time. The FT bit

is cleared on power-down.

For more information on calibration, see the application note AN934, “TIMEKEEPER

calibration.”

3.6

Watchdog timer

The watchdog timer can be used to detect an out-of-control microprocessor. The user

programs the watchdog timer by setting the desired amount of time-out into the eight-bit

watchdog register, address 7FF7h. The five bits (BMB4-BMB0) that store a binary multiplier

determined to be the multiplication of the five-bit multiplier value with the resolution. (For

example: writing 00001110 in the watchdog register = 3x1, or 3 seconds).

Note:

Accuracy of timer is within ± the selected resolution.

If the processor does not reset the timer within the specified period, the M48T37Y/V sets the

watchdog flag (WDF) and generates a watchdog interrupt or a microprocessor reset. WDF

is reset by reading the flags register (Address 7FF0h).

Note:

User must transition address (or toggle chip enable) to see flag bit change.

Reset will not occur unless the addresses are stable at the flag location for at least 15 ns

while the device is in the READ mode as shown in Figure 9 on page 19.

The most significant bit of the watchdog register is the watchdog steering bit. When set to a

'0,' the watchdog will activate the IRQ/FT pin when timed-out. When WDS is set to a '1,' the

register, the FT bit, AFE bit, and ABE bit will reset to a '0' at the end of a watchdog time-out

when the WDS bit is set to a '1.'

The watchdog timer resets when the microprocessor performs a re-write of the watchdog

register or an edge transition (low to high / high to low) on the WDI pin occurs. The timeout

period then starts over.