ARRIAGX_09 datasheet(70/234 Pages) ALTERA

Part #	ARRIAGX

Description	The ArriaTM GX family of devices combines 3.125 gigabits per second (Gbps) serial transceivers

PDF	234 Pages

Scroll/Zoom	100%

Manufacturer	ALTERA [Altera Corporation]

Direct Link	http://www.altera.com

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70 / 234 page

2–64

Chapter 2: Arria GX Architecture

Digital Signal Processing Block

Arria GX Device Handbook, Volume 1

Altera Corporation

A bus of 44 control signals feeds the entire DSP block. These signals include clocks,

asynchronous clears, clock enables, signed and unsigned control signals, addition and

subtraction control signals, rounding and saturation control signals, and accumulator

synchronous loads. The clock signals are routed from LAB row clocks and are

generated from specific LAB rows at the DSP block interface. The LAB row source for

control signals, data inputs, and outputs is shown in Table 2–15.

f For more information about DSP blocks, refer to the DSP Blocks in Arria GX Devices

chapter.

Figure 2–53. DSP Block Interface to Interconnect

LAB

Row Interface

Block

DSP Block

Row Structure

OA[17..0]

OB[17..0]

A[17..0]

B[17..0]

DSP Block to

LAB Row Interface

Block Interconnect Region

36 Inputs per Row

36 Outputs per Row

R4 Interconnect

C4 Interconnect

Direct Link Interconnect

from Adjacent LAB

Direct Link Outputs

to Adjacent LABs

Direct Link Interconnect

from Adjacent LAB

Control

ARRIAGX Datasheet(PDF) 70 Page - Altera Corporation