M95256-CS6TGSLASHK datasheet(22/48 Pages) STMICROELECTRONICS

22 / 48 page

Instructions

M95256-DR, M95256, M95256-W, M95256-R

22/48

Doc ID 12276 Rev 11

Figure 12.

Page Write (WRITE) sequence

The most significant address bit (b15) is Don’t Care.

5.6.1

ECC (error correction code) and Write cycling

The M95256 and M95256-D devices offer an ECC (error correction code) logic which

compares each 4-byte word with its associated 6 EEPROM bits of ECC. As a result, if a

single bit out of 4 bytes of data happens to be erroneous during a Read operation, the ECC

detects it and replaces it by the correct value. The read reliability is therefore much improved

by the use of this feature.

Note however that even if a single byte has to be written, 4 bytes are internally modified

(plus the ECC bits), that is, the addressed byte is cycled together with the three other bytes

making up the word. It is therefore recommended to write data in words (4 bytes) in order to

optimize the number of Write cycles.

The M95256 and M95256-D devices are qualified at 1 million (1 000 000) Write cycles,

using a cycling routine that writes to the device in multiples of 4-byte words.

AI01796D

35 36 37 38 39 40 41 42

44 45 46 47

3456789 10

20 21 22 23 24 25 26 27

14 13

3210

28 29 30

Instruction

16-Bit Address

765432

Data Byte 1

765432

Data Byte 2

765432

Data Byte 3

65432

Data Byte N

M95256-CS6TG/K Datasheet(PDF) 22 Page - STMicroelectronics