IR3500A datasheet(21/48 Pages) IRF

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IR3500A

Page 21 of 48

July 28, 2009

Figure 11 depicts start-up sequence of converter with VR 11 VID with boot voltage, which is selected by VIDSEL pin

based on Table 1. If there is no fault, the SS/DEL pin will start charging when the enable crosses the threshold. The

error amplifier output EAOUT is clamped low until SS/DEL reaches 1.4V. The error amplifier will then regulate the

converter’s output voltage to match the SS/DEL voltage less the 1.4V offset until the converter output reaches the

1.1V boot voltage. The SS/DEL voltage continues to increase until it rises above the 3.0V threshold of VID delay

comparator. The VID set inputs are then activated and VDAC pin transitions to the level determined by the VID

inputs. The SS/DEL voltage continues to increase until it rises above 3.92V and allows the PGOOD signal to be

asserted. SS/DEL finally settles at 4.0V, indicating the end of the soft start.

Figure 12 shows start-up sequence of converter VR 11 VID without boot voltage or AMD Opteron, AMD 6-bit VID

which is selected by VIDSEL pin based on Table 1. If there is no fault, the SS/DEL pin will start charging. The error

amplifier output EAOUT is clamped low until SS/DEL reaches 1.4V. The error amplifier will then regulate the

converter’s output voltage to match the SS/DEL voltage less the 1.4V offset until the converter output reaches the

level determined by the VID inputs. The SS/DEL voltage continues to increase until it rises above 3.92V and allows

the PGOOD signal to be asserted. SS/DEL finally settles at 4.0V, indicating the end of the soft start.

SOFT START

TIME (TD2)

TD5

VRRDY

3.92V

SS/DEL

(12V)

START DELAY (TD1)

VCC

ENABLE

1.4V

VOUT

4.0V

VID SAMPLE

TIME (TD3)

VDAC

NORMAL OPERATION

TD4

VRRDY DELAY

TIME (TD4+TD5)

1.1V

VID

EAOUT

Figure 11 - Start-up sequence of converter with boot voltage

VCCL under voltage lock-out, VID fault modes, over current, as well as a low signal on the ENABLE input

immediately sets the fault latch, which causes the EAOUT pin to drive low turning off the phase IC drivers. The

PGOOD pin also drives low, and SS/DEL begin to discharge until the voltage reaches 0.2V. If the fault has cleared

the fault latch will be reset by the discharge comparator allowing a normal soft start to occur.

Other fault conditions, such as over voltage, open sense lines, open loop monitor, and open daisy chain, set

different fault latches, which start discharging SS/DEL, pull down EAOUT voltage and drive PGOOD low. However,

the latches can only be reset by cycling VCCL power.

IR3500A Datasheet(PDF) 21 Page - International Rectifier

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