Data Sheet

8

Rev. 3.4, 2007-08-16

TLE 6711

Circuit Description

4

Circuit Description

Below some important sections of the TLE 6711 G/GL are described in more detail.

4.1

Power On Reset

In order to avoid any system failure, a sequence of several conditions has to be passed. In case of

V

down (

V

When the level of

V

time

t

reaction time

t

reaction time

t

Figure 4

Reset Function

4.2

Watchdog Operation

The watchdog uses one hundred of the oscillator’s clock signal period as a timebase, defined as the watchdog

cycle time

t

After power-on, the reset output signal at the RO pin (microcontroller reset) is kept LOW for the reset delay time

t

t

shown below. After the closed window the open window with the duration

t

at minimum until the trigger process has occurred, at maximum

t

A HIGH to LOW transition of the watchdog trigger signal on pin WDI is taken by a trigger. To avoid wrong triggering

due to parasitic glitches two HIGH samples followed by two LOW samples (sample period

t

valid trigger. If a trigger signal appears at the watchdog input pin WDI during the open window or a power up/down

occurs, the watchdog window signal is reset and a new closed window follows.

A reset is generated (RO goes LOW) if there is no trigger pulse during the open window or if a pretrigger occurs

during the closed window. This reset happens after 64 cycles after the latest valid closed window start time and

lasts for further 64 cycles.

The triggering is correct also, if the first three samples (two HIGH one LOW) of the trigger pulse at pin WDI are

inside the closed window and only the fourth sample (the second LOW sample) is taken in the open window.

In addition to the microcontroller reset signal RO the device generates a system enable signal at pin SEN. If RO

AET02950

L

H

RO

V

CC

Invalid

RT

V

typ. 4.65 V

t

t

Start-Up

ON Delay

Invalid

Invalid

ON Delay

Started

Stopped

RD

t

RR

t

RD

t

t

t

Power

Start-Up

Normal

Failed

N

Failed

Normal

1 V

ON Delay