Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

TLE6220GP Datasheet(PDF) 5 Page - Infineon Technologies AG

Part # TLE6220GP
Description  Smart Quad Low-Side Switch Short Circuit Protection
PDF  19 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  INFINEON [Infineon Technologies AG]
Direct Link  http://www.infineon.com
Logo INFINEON - Infineon Technologies AG

TLE6220GP Datasheet(HTML) 5 Page - Infineon Technologies AG

  TLE6220GP_07 Datasheet HTML 1Page - Infineon Technologies AG TLE6220GP_07 Datasheet HTML 2Page - Infineon Technologies AG TLE6220GP_07 Datasheet HTML 3Page - Infineon Technologies AG TLE6220GP_07 Datasheet HTML 4Page - Infineon Technologies AG TLE6220GP_07 Datasheet HTML 5Page - Infineon Technologies AG TLE6220GP_07 Datasheet HTML 6Page - Infineon Technologies AG TLE6220GP_07 Datasheet HTML 7Page - Infineon Technologies AG TLE6220GP_07 Datasheet HTML 8Page - Infineon Technologies AG TLE6220GP_07 Datasheet HTML 9Page - Infineon Technologies AG Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 19 page
background image
Data Sheet TLE 6220 GP
V2.1
Page
2007-05-03
5
Electrical Characteristics cont.
Parameter and Conditions
Symbol
Values
Unit
VS = 4.5 to 5.5 V ; Tj = - 40 °C to + 150 °C ; Reset = H
(unless otherwise specified)
min
typ
max
5. Diagnostic Functions
Open Load Detection Voltage
VDS(OL)
VS -2.5 VS -2
VS -1.3
V
Output Pull Down Current
IPD(OL)
50
90
150
µA
Fault Delay Time
td(fault)
50
110
200
µs
Short to Ground Detection Voltage
VDS(SHG)
VS –3.3 VS -2.9 VS -2.5
V
Short to Ground Detection Current
ISHG
-50
-100
-150
µA
6. SPI-Timing
Serial Clock Frequency (depending on SO load)
fSCK
DC
--
5
MHz
Serial Clock Period (1/fclk)
t
p(SCK)
200
--
--
ns
Serial Clock High Time
t
SCKH
50
--
--
ns
Serial Clock Low Time
t
SCKL
50
--
--
ns
Enable Lead Time (falling edge of CS to rising edge of CLK)
t
lead
250
--
--
ns
Enable Lag Time (falling edge of CLK to rising edge ofCS )
t
lag
250
---
--
ns
Data Setup Time (required time SI to falling of CLK)
t
SU
20
--
--
ns
Data Hold Time (falling edge of CLK to SI)
t
H
20
--
--
ns
Disable Time @ CL = 50 pF
8
tDIS
--
--
150
ns
Transfer Delay Time
7
( CS high time between two accesses)
tdt
200
--
--
ns
Data Valid Time
CL = 50 pF
CL = 100 pF
8
CL = 220 pF
8
tvalid
--
--
--
--
--
--
110
120
150
ns
7 This time is necessary between two write accesses. To get the correct diagnostic information, the transfer
delay time has to be extended to the maximum fault delay time td(fault)max = 200µs.
8 This parameter will not be tested but guaranteed by design



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com