iC-MB3

BiSS INTERFACE MASTER, 1-Chan./3-Slaves

Rev D1, Page 11/26

Figure 10: Timing diagram of SSI mode.

OPERATING REQUIREMENTS: BiSS Interface (SSI mode)

Operating conditions: Register bit SELSSI = 1;

VDD = 3 ... 5.5 V, Ta = -25 ... 85 °C; input levels lo = 0 ... 0.45 V, hi = 2.4 V ... VDD

Item

Symbol

Parameter

Conditions

Fig.

Unit

Min.

Max.

l80

Clock Period

FreqSens über FREQ(4:0) selected in

accordance with table on page 17

10

2

320

l81

Clock Signal Hi Level Duration

10

50

l82

Clock Signal Lo Level Duration

10

50

l83

Setup Time:

SL1 stable before MA1 lo

6hi

10

30

ns

l83

Hold Time:

SL1 stable before MA1 lo

6hi

10

10

ns

Evaluating SL1 Signals

In BiSS interface SSI mode SL1 values are sampled with the rising edge at MA1. An overall delay of the sensor

response to the clock at MA1, caused by process times in the sensor or transmission times, is permissible up to

the length of one clock cycle.