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STM8L101F2P6TR Datasheet(PDF) 34 Page - STMicroelectronics |
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STM8L101F2P6TR Datasheet(HTML) 34 Page - STMicroelectronics |
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34 / 81 page  Option bytes STM8L101xx 34/81 Doc ID 15275 Rev 11 7 Option bytes Option bytes contain configurations for device hardware features as well as the memory protection of the device. They are stored in a dedicated row of the memory. All option bytes can be modified only in ICP mode (with SWIM) by accessing the EEPROM address. See Table 10 for details on option byte addresses. Refer to the STM8L Flash programming manual (PM0054) and STM8 SWIM and Debug Manual (UM0320) for information on SWIM programming procedures. Table 10. Option bytes Addr. Option name Option byte No. Option bits Factory default setting 76 54 3 2 1 0 0x4800 Read-out protection (ROP) OPT1 ROP[7:0] 0x00 0x4807 - - Must be programmed to 0x00 0x00 0x4802 UBC (User Boot code size) OPT2 UBC[7:0] 0x00 0x4803 DATASIZE OPT3 DATASIZE[7:0] 0x00 0x4808 Independent watchdog option OPT4 [1:0] Reserved IWDG _HALT IWDG _HW 0x00 Table 11. Option byte description OPT1 ROP[7:0] Memory readout protection (ROP) 0xAA: Enable readout protection (write access via SWIM protocol) Refer to Read-out protection section in the STM8L reference manual (RM0013) for details. OPT2 UBC[7:0] Size of the user boot code area 0x00: no UBC 0x01-0x02: UBC contains only the interrupt vectors. 0x03: Page 0 and 1 reserved for the interrupt vectors. Page 2 is available to store user boot code. Memory is write protected ... 0x7F - Page 0 to 126 reserved for UBC, memory is write protected Refer to User boot area (UBC) section in the STM8L reference manual (RM0013) for more details. |
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