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MPC5668X Datasheet(PDF) 56 Page - Freescale Semiconductor, Inc

Part # MPC5668X
Description  MPC5668x Microcontroller Data Sheet
PDF  66 Pages
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Manufacturer  FREESCALE [Freescale Semiconductor, Inc]
Direct Link  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

MPC5668X Datasheet(HTML) 56 Page - Freescale Semiconductor, Inc

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MPC5668x Microcontroller Data Sheet, Rev. 5
Electrical Characteristics
Freescale Semiconductor
56
10
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz
0—
tmckl
ns
11
Bus Hold time3
tmdzh
4—
—
ns
12
MLBSIG/MLBDAT output valid from
MLBCLK rising
tmcrdv
——
8
ns
• Ground = 0.0V
• Load Capacitance = 60 pF, SIU_PCR144–SIU_PCR146[DSC] = 0b11.
• MLB speed of 256 Fs or 512 Fs (Fs = 48 kHz)
Unless otherwise noted, all timing parameters are specified from the valid voltage threshold in Table 30.
1 The Controller can shut off MLBCLK to place MLB in a low-power state.
2 Pulse width variation is measured at 1.25 V by triggering on one edge of MLBCLK and measuring the spread on the other
edge, measured in ns peak-to-peak (ns p-p).
3 The board must be designed to insure that the high-impedance bus does not leave the logic state of the final driven bit for this
time period. Therefore, coupling must be minimized while meeting the maximum capacitive load listed.
Table 32. MLB Timing for MLB Speed 1024 Fs
Spec
Parameter
Symbol
Min
Typ
Max
Unit
Comments
1
MLBCLK Operating Frequency1
fmck
45.056
—
—
—
—
49.152
—
—
—
—
49.2544
51.200
MHz
1024 Fs at 44.0 kHz
1024 Fs at 48.0 kHz
1024 Fs at 48.1 kHz
1024 Fs PLL unlocked
2
MLBCLK rise time
tmckr
——
1
ns
VIL to VIH
3
MLBCLK fall time
tmckf
——
1
ns
VIH to VIL
4
MLBCLK cycle time
tmckc
—
20.3
—
ns
VIL to VIH
5
MLBCLK low time
tmckl
6.5
6.1
7.7
7.3
—ns
1024 Fs
PLL unlocked
6
MLBCLK high time
tmckh
9.7
9.3
10.6
10.2
—ns
1024 Fs
PLL unclocked
7
MLBCLK pulse width variation2
tmpwv
—
—
0.7
ns p-p
8
MLBSIG/MLBDAT input valid to
MLBCLK falling
tdsmcf
1—
—
ns
9
MLBSIG/MLBDAT input hold from
MLBCLK low
tdhmcf
0—
—
ns
10
MLBSIG/MLBDAT output high
impedance from MLBCLK low
tmcfdz
0—
tmckl
ns
11
Bus Hold time3
tmdzh
2—
—
ns
12
MLBSIG/MLBDAT output valid from
MLBCLK rising
tmcrdv
——
7
ns
• Ground = 0.0V
• Load Capacitance = 40 pF, SIU_PCR144–SIU_PCR146[DSC] = 0b00.
• MLB speed = 1024Fs (Fs = 48 kHz)
• Unless otherwise noted, timing parameters are specified from the valid voltage threshold in Table 30.
Table 31. MLB Timing for MLB Speed 256 Fs or 512 Fs (continued)
Spec
Parameter
Symbol
Min
Typ
Max
Unit
Comments



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