K20P100M100SF2 datasheet(21/65 Pages) FREESCALE

21 / 65 page

Table 11. JTAG limited voltage range electricals (continued)

Symbol

Description

Min.

Max.

Unit

TCLK cycle period

1/J1

—

TCLK clock pulse width

• Boundary Scan

• JTAG and CJTAG

• Serial Wire Debug

—

TCLK rise and fall times

—

Boundary scan input data setup time to TCLK rise

—

Boundary scan input data hold time after TCLK rise

—

TCLK low to boundary scan output data valid

—

TCLK low to boundary scan output high-Z

—

TMS, TDI input data setup time to TCLK rise

—

J10

TMS, TDI input data hold time after TCLK rise

—

J11

TCLK low to TDO data valid

—

J12

TCLK low to TDO high-Z

—

J13

TRST assert time

100

—

J14

TRST setup time (negation) to TCLK high

—

Table 12. JTAG full voltage range electricals

Symbol

Description

Min.

Max.

Unit

Operating voltage

1.71

3.6

TCLK frequency of operation

• Boundary Scan

• JTAG and CJTAG

• Serial Wire Debug

MHz

TCLK cycle period

1/J1

—

TCLK clock pulse width

• Boundary Scan

• JTAG and CJTAG

• Serial Wire Debug

12.5

—

TCLK rise and fall times

—

Boundary scan input data setup time to TCLK rise

—

Boundary scan input data hold time after TCLK rise

—

TCLK low to boundary scan output data valid

—

TCLK low to boundary scan output high-Z

—

Table continues on the next page...

Peripheral operating requirements and behaviors

K20 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011.

Freescale Semiconductor, Inc.

Preliminary

K20P100M100SF2 Datasheet(PDF) 21 Page - Freescale Semiconductor, Inc

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