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K40P81M100SF2 Datasheet(PDF) 13 Page - Freescale Semiconductor, Inc |
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K40P81M100SF2 Datasheet(HTML) 13 Page - Freescale Semiconductor, Inc |
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13 / 63 page ![]() • CPU and system clocks = 100 MHz • Bus clock = 50 MHz • Flash clock = 25 MHz Table 5. Power mode transition operating behaviors Symbol Description Min. Max. Unit Notes tPOR After a POR event, amount of time from the point VDD reaches 1.8V to execution of the first instruction across the operating temperature range of the chip. — 300 μs 1 RUN → VLLS1 → RUN • RUN → VLLS1 • VLLS1 → RUN — — 4.1 123.8 μs μs RUN → VLLS2 → RUN • RUN → VLLS2 • VLLS2 → RUN — — 4.1 49.3 μs μs RUN → VLLS3 → RUN • RUN → VLLS3 • VLLS3 → RUN — — 4.1 49.2 μs μs RUN → LLS → RUN • RUN → LLS • LLS → RUN — — 4.1 5.9 μs μs RUN → STOP → RUN • RUN → STOP • STOP → RUN — — 4.1 4.2 μs μs RUN → VLPS → RUN • RUN → VLPS • VLPS → RUN — — 4.1 5.8 μs μs 1. Normal boot (FTFL_OPT[LPBOOT]=1) 5.1.5 Power consumption operating behaviors Table 6. Power consumption operating behaviors Symbol Description Min. Typ. Max. Unit Notes IDDA Analog supply current — — TBD mA 1 Table continues on the next page... General K40 Sub-Family Data Sheet Data Sheet, Rev. 4, 3/2011. Freescale Semiconductor, Inc. Preliminary 13 |
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