CY8C36 datasheet(73/112 Pages) CYPRESS

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PRELIMINARY

PSoC® 3: CY8C36 Family Datasheet

Document Number: 001-53413 Rev. *I

Page 73 of 112

11.5.2 Delta-Sigma ADC

Unless otherwise specified, operating conditions are:

Operation in continuous sample mode

fclk = 6.144 MHz

Reference = 1.024 V internal reference bypassed on P3.2 or P0.3

Unless otherwise specified, all charts and graphs show typical values

Table 11-12. 12-bit Delta-sigma ADC DC Specifications

Parameter

Description

Conditions

Min

Typ

Max

Units

Resolution

–

bits

Number of channels, single ended

–

No. of

GPIO

–

Number of channels, differential

Differential pair is formed using a

pair of GPIOs.

––

No. of

GPIO/2

–

Monotonic

Yes

–

Gain error

Buffered, buffer gain = 1,

modulator gain = 1, 25 °C

––

±0.2

Gain drift

Buffered, buffer gain = 1,

modulator gain = 1

–

ppm/°C

Vos

Input offset voltage

Buffered

–

±0.1

TCVos

Temperature coefficient, input offset

voltage

Buffered

–

µV/°C

Input voltage range, single ended[38]

VSSA

–VDDA

Input voltage range, differential unbuf-

fered[38]

VSSA

–VDDA

Input voltage range, differential,

buffered[38]

VSSA

–VDDA – 1

INL12

Integral non linearity[38]

Range = ±1.024 V, unbuffered

–

±1

LSB

DNL12

Differential non linearity[38]

Range = ±1.024 V, unbuffered

–

±1

LSB

INL8

Integral non linearity[38]

Range = ±1.024 V, unbuffered

–

±1

LSB

DNL8

Differential non linearity[38]

Range = ±1.024 V, unbuffered

–

±1

LSB

Rin_Buff

ADC input resistance

Input buffer used

–

Rin_ADC12 ADC input resistance

Input buffer bypassed, 12 bit, Range

= ±1.024 V

–148[39]

–k

Cin_G1

ADC input capacitance[38]

Gain = 1

–

Vextref

ADC external reference input voltage, see

also internal reference in Voltage

Reference on page 75

Pins P0[3], P3[2]

0.9

–

1.3

Current Consumption

IDD_12

Current consumption, 12 bit[38]

192 ksps, unbuffered

–

1.4

IBUFF

Buffer current consumption[38]

––

2.5

Notes

38. Based on device characterization (not production tested).

39. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to

the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.

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