3

Integrated

Circuit

Systems, Inc.

ICS9LPRS545

Datasheet

1479A—07/28/09

SSOP/TSSOP Pin Description (Continued)

25

PCI_STOP#/SRCT5_LPR

I/O

Stops all PCICLKs at logic 0 level, when low. Can also stop SRC clocks. Free running PCICLKs are not effected by this

input. / True clock of push-pull SRC pair with int. 33ohm series resistor.

26

VDDSRC

PWR Supply for SRC clocks, 3.3V nominal

27

GNDSRC

PWR Ground pin for the SRC outputs

28

SRCC7_LPR/CR#_E

I/O

Complementary clock of push-pull SRC output with int. 33ohm series resistor/CR#_E input. Disable SRC7 via Byte 3, bit 3

before using as CR#_E.

Byte 6, bit 7: 0=SRC7 (default), 1=CR#_E

Outputs controlled by CR#_E are not present on this device

29

SRCT7_LPR/CR#_F

I/O

True clock of push-pull SRC output with int. 33 ohm series resistor/CR#_F input. Disable SRC7 via Byte 3, bit 3 before

using CR#_F.

Byte 6, bit 6: 0 = SRC7 (default),1 = CR#_F enabled to control SRC8.

30

VDDSRC_IO

PWR

1.05V to 3.3V from external power supply

31

CPUC2_ITP_LPR/SRCC8_LPR OUT

Complementary clock of low power differential CPU2_ITP/SRC pair. No Rs needed. The function of this pin is determined

by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:

Pin 7 latched input Value

0 = SRC8#

1 = ITP#

32

CPUT2_ITP_LPR/SRCT8_LPR

OUT

True clock of low power differential CPU2_ITP/SRC8 pair. No Rs needed. The function of this pin is determined by the

latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:

Pin 7 latched input Value

0 = SRC8

1 = ITP

33

VDDCPU_IO

PWR

1.05V to 3.3V from external power supply

34

CPUC1_LPR_F

OUT

Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. Free running

during iAMT. No 50ohm resistor to GND needed.

35

CPUT1_LPR_F

OUT

True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. Free running during

iAMT No 50 ohm resistor to GND needed.

36

GNDCPU

PWR Ground pin for the CPU outputs

37

CPUC0_LPR

OUT

Complementary clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. No 50 ohm

resistor to GND needed.

38

CPUT0_LPR

OUT

True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm series resistor. No 50 ohm resistor to

GND needed.

39

VDDCPU

PWR Supply for CPU clocks, 3.3V nominal

40

CK_PWRGD/PD#

IN

Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode

41

FSLB/TEST_MODE

IN

3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values.

TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in test mode. Refer to Test

Clarification Table.

42

GNDREF

PWR Ground pin for the REF outputs.

43

X2

OUT Crystal output, Nominally 14.318MHz

44

X1

IN

Crystal input, Nominally 14.318MHz.

45

VDDREF

PWR Ref, XTAL power supply, nominal 3.3V

46

REF0/FSLC/TEST_SEL

I/O

14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for

Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched input to enable test mode. Refer to Test Clarification Table

47

SDATA

I/O

Data pin for SMBus circuitry, 3.3V tolerant.

48

SCLK

IN

Clock pin of SMBus circuitry, 5V tolerant.