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DSPIC30F2010 Datasheet(PDF) 194 Page - Microchip Technology |
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DSPIC30F2010 Datasheet(HTML) 194 Page - Microchip Technology |
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194 / 202 page  dsPIC30F2010 DS70118J-page 194 © 2011 Microchip Technology Inc. Width ........................................................................... 26 Data EEPROM Memory ...................................................... 49 Erasing ........................................................................ 50 Erasing, Block ............................................................. 50 Erasing, Word ............................................................. 50 Protection Against Spurious Write .............................. 52 Reading....................................................................... 49 Write Verify ................................................................. 52 Writing ......................................................................... 51 Writing, Block .............................................................. 52 Writing, Word .............................................................. 51 DC Characteristics ............................................................ 148 BOR .......................................................................... 155 Brown-out Reset ....................................................... 154 I/O Pin Input Specifications ....................................... 153 I/O Pin Output Specifications .................................... 154 Idle Current (IIDLE) .................................................... 151 Operating Current (IDD)............................................. 150 Power-Down Current (IPD) ........................................ 152 Program and EEPROM............................................. 155 Temperature and Voltage Specifications .................. 148 Dead-Time Generators ....................................................... 86 Ranges........................................................................ 86 Development Support ....................................................... 143 Device Configuration Register Map............................................................. 133 Device Configuration Registers......................................... 132 FBORPOR ................................................................ 132 FGS........................................................................... 132 FOSC ........................................................................ 132 FWDT........................................................................ 132 Device Overview ................................................................... 7 Divide Support..................................................................... 14 DSP Engine......................................................................... 14 Multiplier...................................................................... 16 Dual Output Compare Match Mode .................................... 72 Continuous Pulse Mode .............................................. 72 Single Pulse Mode ...................................................... 72 E Edge-Aligned PWM............................................................. 85 Electrical Characteristics................................................... 147 AC ............................................................................. 156 DC ............................................................................. 148 Equations A/D Conversion Clock ............................................... 113 Baud Rate ................................................................. 107 PWM Period ................................................................ 84 PWM Period (Up/Down Count Mode) ......................... 84 PWM Resolution ......................................................... 84 Serial Clock Rate ........................................................ 99 Errata .................................................................................... 6 Exception Sequence Trap Sources .............................................................. 39 External Clock Timing Characteristics Type A and B Timer .................................................. 163 External Clock Timing Requirements................................ 157 Type A Timer ............................................................ 163 Type B Timer ............................................................ 164 Type C Timer ............................................................ 164 External Interrupt Requests ................................................ 41 F Fast Context Saving............................................................ 41 Firmware Instructions........................................................ 135 Flash Program Memory....................................................... 43 In-Circuit Serial Programming (ICSP)......................... 43 Run-Time Self-Programming (RTSP) ......................... 43 Table Instruction Operation Summary ........................ 43 I I/O Pin Specifications Input.......................................................................... 153 Output ....................................................................... 154 I/O Ports.............................................................................. 53 Parallel I/O (PIO) ........................................................ 53 I2C....................................................................................... 95 I2C 10-bit Slave Mode Operation........................................ 97 Reception ................................................................... 98 Transmission .............................................................. 97 I2C 7-bit Slave Mode Operation.......................................... 97 Reception ................................................................... 97 Transmission .............................................................. 97 I2C Master Mode Baud Rate Generator ................................................. 99 Clock Arbitration ....................................................... 100 Multi-Master Communication, Bus Collision and Bus Arbitration ........................................... 100 Reception ................................................................... 99 Transmission .............................................................. 99 I2C Module Addresses................................................................... 97 Bus Data Timing Characteristics Master Mode..................................................... 176 Slave Mode....................................................... 178 Bus Data Timing Requirements Master Mode..................................................... 177 Slave Mode....................................................... 179 Bus Start/Stop Bits Timing Characteristics Master Mode..................................................... 176 Slave Mode....................................................... 178 General Call Address Support .................................... 99 Interrupts .................................................................... 98 IPMI Support............................................................... 99 Master Operation ........................................................ 99 Master Support ........................................................... 99 Operating Function Description .................................. 95 Operation During CPU Sleep and Idle Modes .......... 100 Pin Configuration ........................................................ 95 Programmer’s Model .................................................. 95 Register Map ............................................................ 101 Registers .................................................................... 95 Slope Control .............................................................. 99 Software Controlled Clock Stretching (STREN = 1) ... 98 Various Modes............................................................ 95 Idle Current (IIDLE) ............................................................ 151 In-Circuit Serial Programming (ICSP)............................... 121 Independent PWM Output .................................................. 87 Initialization Condition for RCON Register Case 1 ........... 130 Initialization Condition for RCON Register Case 2 ........... 130 Initialization Condition for RCON Register, Case 1 .......... 130 Input Capture (CAPx) Timing Characteristics ................... 166 Input Capture Interrupts...................................................... 69 Register Map .............................................................. 70 Input Capture Module ......................................................... 67 In CPU Sleep Mode .................................................... 69 Simple Capture Event Mode....................................... 68 Input Capture Timing Requirements................................. 166 Input Change Notification Module....................................... 54 Register Map (bits 15-0) ............................................. 55 Input Characteristics QEA/QEB ................................................................. 169 |
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