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HT68F03 Datasheet(PDF) 96 Page - Holtek Semiconductor Inc |
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HT68F03 Datasheet(HTML) 96 Page - Holtek Semiconductor Inc |
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96 / 147 page  HT66F03/HT66F04/HT68F03/HT68F04 Rev. 1.30 96 February 17, 2011 Counter Value CCRA TnON TnPAU TnBPOL CCRA Int. Flag TnAF CCRB Int. Flag TnBF Time Pause Resume Stop Counter Restart TnCCLR = 1; TnBM [1:0] = 10; TnPWM [1:0] = 11 Output Pin Reset to Initial value Output controlled by other pin-shared function CCRB TPnB Pin (TnBOC=1) TPnB Pin (TnBOC=0) Duty Cycle set by CCRB PWM Period set by CCRA Output Inverts when TnBPOL is high CCRP Int. Flag TnPF ETM PWM Mode -- Centre Aligned Note: 1. Here TnCCLR=1 therefore CCRA clears the counter and determines the PWM period 2. TnPWM [1:0] =11 therefore the PWM is centre aligned 3. The internal PWM function continues running even when TnBIO [1:0] = 00 or 01 4. CCRA controls the TPnB PWM period and CCRB controls the TPnB PWM duty 5. CCRP will generate an interrupt request when the counter decrements to its zero value |
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