MCP7940N datasheet(13/36 Pages) MICROCHIP

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 2011 Microchip Technology Inc.

DS25010A-page 13

MCP7940N

4.2.2

MFP

Pin 7 is a multi-function pin and supports the following

functions:

• Use of the OUT bit in the Control register for

single bit I/O

• Alarm Outputs – Available in VBAT mode

• FOUT mode – driven from a FOSC divider – Not

available in VBAT mode

The internal control logic for the MFP is connected to

the switched internal supply bus, this allows operation

in VBAT mode. The Alarm Output is the only mode that

operates in VBAT mode, other modes are suspended.

4.2.3

VBAT

If the VBAT feature is not being used, the VBAT pin

should be connected to GND. A low-value series

resistor is recommended between the external battery

and the VBAT pin.

The VBAT point is defined as 1.5V typical. When VDD

falls below 1.5V the system will continue to operate

the RTCC and SRAM using the VBAT supply. The

following conditions apply:

4.2.4

CRYSTAL SPECS

The MCP7940N has been designed to operate with a

standard 32 kHz crystal. Devices with a specified load

capacitance of either 12pF or 6pF can be used. The

end user should fully validate the chosen crystal across

all the expected design parameters of the system to

ensure correct operation.

The following crystals have been tested and shown to

work with the MCP7940N:

• CM200S 12pF surface mount crystals from

Citizen

• ECS-.327 12pF surface mount crystals from ECS

INC

• CFS206 12pF leaded crystals from Citizen

This is not a definitive list and all crystals should be

tested in the target application across all temperature,

voltage and other significant environmental conditions.

4.2.5

POWER-FAIL TIME-STAMP

The MCP7940N family of RTCC devices feature a

power-fail time-stamp feature. This feature will save

the time at which VCC crosses the VTRIP voltage. To

use this feature, a VBAT supply must be present and

the oscillator must also be running.

There are two separate sets of registers that are used

to record this information:

• The first set located at 0x18h through 0x1Bh are

loaded at the time when VCC fails and the RTCC

operates on the VBAT. The VBAT (register 0x03h

bit 4) bit is also set at this time.

• The second set of registers, located at 0x1Ch

through 0x1Fh, are loaded at the time when VCC

is restored and the RTCC switches to VCC.

The power-fail time-stamp registers are cleared when

the VBAT bit is cleared in software.

TABLE 4-2:

Supply

Condition

Read/Write

Access

Powered

VCC < VTRIP, VCC < VBAT

VBAT

VCC > VTRIP, VCC < VBAT

Yes

VCC

VCC > VTRIP, VCC > VBAT

Yes

VCC

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