70592C datasheet(26/314 Pages) MICROCHIP

26 / 314 page

PIC24HJXXXGPX06A/X08A/X10A

DS70592C-page 26

2.7

Oscillator Value Conditions on

Device Start-up

If the PLL of the target device is enabled and

configured for the device start-up oscillator, the

maximum oscillator source frequency must be limited

≤8 MHz for start-up with PLL enabled to comply with

device PLL start-up conditions. This means that if the

external oscillator frequency is outside this range, the

application must start-up in the FRC mode first. The

default PLL settings after a POR with an oscillator

frequency outside this range will violate the device

operating speed.

Once the device powers up, the application firmware

can initialize the PLL SFRs, CLKDIV and PLLDBF to a

suitable value, and then perform a clock switch to the

Oscillator + PLL clock source. Note that clock switching

must be enabled in the device Configuration word.

2.8

Configuration of Analog and

Digital Pins During ICSP

Operations

If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a

debugger, it automatically initializes all of the A/D input

pins (ANx) as “digital” pins, by setting all bits in the

AD1PCFGL register.

The bits in this register that correspond to the A/D pins

that are initialized by MPLAB ICD 2, ICD 3, or REAL

ICE, must not be cleared by the user application

firmware; otherwise, communication errors will result

between the debugger and the device.

If your application needs to use certain A/D pins as

analog input pins during the debug session, the user

application must clear the corresponding bits in the

AD1PCFGL register during initialization of the ADC

module.

When MPLAB ICD 2, ICD 3 or REAL ICE is used as a

programmer, the user application firmware must

correctly configure the AD1PCFGL register. Automatic

initialization of this register is only done during

debugger operation. Failure to correctly configure the

analog input pins, resulting in the port value being read

as a logic ‘0’, which may affect user application

functionality.

2.9

Unused I/Os

Unused I/O pins should be configured as outputs and

driven to a logic-low state.

Alternatively, connect a 1k to 10k resistor between VSS

and the unused pins.

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