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xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx

Fig 2.

Functional diagram P5CD016/P5CD021/P5CD041/P5CD081

RF

INTERFACE

LA

LB

IO1

IO3

PROGRAMMABLE

IO1, IO2, IO3

IO2

CLK

RST_N

VDD

VSS

CIU

ISO 14443

ROM

264 KB

PROGRAM

MEMORY

SECURE_MX51 CPU

7680 B

DATA

MEMORY

EEPROM

16 KB/20 KB/

52 KB/ 40 KB/

80 KB

DATA AND

PROGRAM

MEMORY

CRC16

001aal386

FAST

RNG

TIMERS

16-bit

T0

16-bit

T1

RAM

FameXE

ENHANCED PUBLIC

KEY

COPROCESSOR e.g.

RSA, ECC

AES

COPROCESSOR

TRIPLE-DES

COPROCESSOR

UART

ISO 7816

CLOCK

FILTER

SECURITY SENSORS

RESET GENERATION

VOLTAGE REGULATOR

MEMORY MANAGEMENT UNIT (MMU)

CLOCK

GENERATION

P5CD016

P5CD021

P5CD041

P5CD081

P5CD051