PCF2123TS datasheet(9/63 Pages) NXP

9 / 63 page

PCF2123

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Product data sheet

Rev. 5 — 27 April 2011

9 of 63

NXP Semiconductors

PCF2123

SPI Real time clock/calendar

8.3 Control registers

8.3.1 Register Control_1

[1]

Default value.

[2]

For a software reset, 01011000 (58h) must be sent to register Control_1 (see Section 8.3.1.1).

8.3.1.1

Reset

A reset is automatically generated at power-on. A reset can also be initiated with the

software reset command. It is generally recommended to make a software reset after

power-on.

A software reset can be initiated by setting the bits 6, 4 and 3 in register Control_1 logic 1

and all other bits logic 0 by sending the bit sequence 01011000 (58h), see Figure 7. If this

bit sequence is not correct, the software reset instruction will be ignored to protect the

device from accidently being reset. When sending the software instruction, the other bits

are not written.

Table 5.

Control_1 - control and status register 1 (address 00h) bit description

Bit

Symbol

Value

Description

Reference

EXT_TEST

0[1]

normal mode

Section 8.10

external clock test mode

unused

5STOP

0[1]

the RTC source clock runs

Section 8.11

the RTC clock is stopped;

RTC divider chain flip-flops are

asynchronously set to logic 0;

CLKOUT at 32.768 kHz, 16.384 kHz or

8.192 kHz is still available

4SR

0[1]

no software reset

Section 8.3.1.1

initiate software reset[2];

this register will always return a 0 when

read

unused

12_24

0[1]

24 hour mode is selected

12 hour mode is selected

1CIE

0[1]

no correction interrupt generated

Section 8.9

interrupt pulses will be generated at every

correction cycle

unused

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