MCP73861T datasheet(21/34 Pages) MICROCHIP

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 2011 Microchip Technology Inc.

DS21893E-page 21

MCP73861/2/3/4

Power dissipation with a 5V, ±10% input voltage source

is:

With the battery charger mounted on a 1 in2 pad of

1 oz. copper, the junction temperature rise is 60°C,

approximately. This would allow for a maximum operat-

ing ambient temperature of 50°C before thermal

regulation is entered.

6.1.1.3

External Capacitors

The MCP7386X is stable with or without a battery load.

In order to maintain good AC stability in the Constant-

voltage mode, a minimum capacitance of 4.7 µF is rec-

ommended to bypass the VBAT pin to VSS. This capac-

itance provides compensation when there is no battery

load. In addition, the battery and interconnections

appear inductive at high frequencies. These elements

are in the control feedback loop during Constant-volt-

age mode. Therefore, the bypass capacitance may be

necessary to compensate for the inductive nature of

the battery pack.

Virtually any good quality output filter capacitor can be

used, independent of the capacitor’s minimum Effec-

tive Series Resistance (ESR) value. The actual value of

the capacitor (and its associated ESR) depends on the

output load current. A 4.7 µF ceramic, tantalum or alu-

minum electrolytic capacitor at the output is usually suf-

ficient to ensure stability for up to a 1A output current.

6.1.1.4

Reverse-Blocking Protection

The MCP7386X provides protection from a faulted or

shorted input, or from a reversed-polarity input source.

Without the protection, a faulted or shorted input would

discharge the battery pack through the body diode of

the internal pass transistor.

6.1.1.5

Enable Interface

In the stand-alone configuration, the enable pin is gen-

erally tied to the input voltage. The MCP7386X auto-

matically enters a Low-power mode when voltage on

the VDD input falls below the UVLO voltage (VSTOP),

reducing the battery drain current to 0.23 µA,typically.

6.1.1.6

Charge Status Interface

Two status outputs provide information on the state of

charge. The current-limited, open-drain outputs can be

used to illuminate external LEDs. Refer to Table 5-1 for

a summary of the state of the status outputs during a

charge cycle.

6.2

PCB Layout Issues

For optimum voltage regulation, place the battery pack

as close as possible to the device’s VBAT and VSS pins,

recommended to minimize voltage drops along the

high current-carrying PCB traces.

If the PCB layout is used as a heatsink, adding many

vias in the heatsink pad can help conduct more heat to

the backplane of the PCB, thus reducing the maximum

junction temperature.

Pow erD issip atio n

5.5V

2.7 V

–

 575mA



1.61 W

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