IMX28CEC datasheet(55/70 Pages) FREESCALE

55 / 70 page

i.MX28 Applications Processors Data Sheet for Consumer Products, Rev. 1

Freescale Semiconductor

3.5.14.2

MMC4.4 (Dual Data Rate) AC Timing

Figure 37 depicts the timing of MMC4.4, and Table 59 lists the MMC4.4 timing characteristics. Be aware

that only DATA0–DATA7 are sampled on both edges of the clock (not applicable to CMD).

Figure 37. MMC4.4 Timing

SD7

SSP Input Setup Time

tISU

2.5

—

SD8

SSP Input Hold Time

tIH

2.5

—

1 In low speed mode, the card clock must be lower than 400 kHz, and the voltage ranges from 2.7 to 3.6 V.

2 In normal speed mode for the SD/SDIO card, clock frequency can be any value between 0 ~ 25 MHz. In high speed mode,

clock frequency can be any value between 0 ~ 50 MHz.

3 In normal speed mode for MMC card, clock frequency can be any value between 0 ~ 20 MHz. In high speed mode, clock

frequency can be any value between 0 ~ 52MHz.

4 To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2ns.

Table 59. MMC4.4 Interface Timing Specification

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

Clock Frequency (MMC Full Speed/High Speed)

fPP

052

MHz

SSP Output / Card Inputs CMD, DAT (Reference to CLK)

SD2

SSP Output Delay

tOD

–5

SSP Input / Card Outputs CMD, DAT (Reference to CLK)

SD3

SSP Input Setup Time

tISU

2.5

—

SD4

SSP Input Hold Time

tIH

2.5

—

Table 58. SD/MMC4.3 Interface Timing Specification (continued)

Parameter

Symbols

Min

Max

Unit

SD1

SD2

SD3

output from SSP to card

DAT1

......

DAT7

DAT0

input from card to SSP

DAT1

......

DAT7

DAT0

SCK

SD4

SD2

......

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